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The union of all files from all check-ins in directory wiki_references/2017/software/simulators/p2psim/src/third_party/libgmp_v_4_1_2/gmp-4.1.2/mpn/x86/p6   [history]

Copyright 2000, 2001 Free Software Foundation, Inc.

This file is part of the GNU MP Library.

The GNU MP Library is free software; you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
License for more details.

You should have received a copy of the GNU Lesser General Public License
along with the GNU MP Library; see the file COPYING.LIB.  If not, write to
the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA.

                      INTEL P6 MPN SUBROUTINES

This directory contains code optimized for Intel P6 class CPUs, meaning
PentiumPro, Pentium II and Pentium III.  The mmx and p3mmx subdirectories
have routines using MMX instructions.


Times for the loops, with all code and data in L1 cache, are as follows.
Some of these might be able to be improved.


	mpn_add_n/sub_n           3.7

	mpn_copyi                 0.75
	mpn_copyd                 1.75 (or 0.75 if no overlap)

	mpn_divrem_1             39.0
	mpn_mod_1                21.5
	mpn_divexact_by3          8.5

	mpn_mul_1                 5.5
	mpn_addmul/submul_1       6.35

	mpn_l/rshift              2.5

	mpn_mul_basecase          8.2 cycles/crossproduct (approx)
	mpn_sqr_basecase          4.0 cycles/crossproduct (approx)
	                          or 7.75 cycles/triangleproduct (approx)

Pentium II and III have MMX and get the following improvements.

	mpn_divrem_1             25.0 integer part, 17.5 fractional part

	mpn_l/rshift              1.75


Write-allocate L1 data cache means prefetching of destinations is unnecessary.

Mispredicted branches have a penalty of between 9 and 15 cycles, and even up
to 26 cycles depending how far speculative execution has gone.  The 9 cycle
minimum penalty comes from the issue pipeline being 9 stages.

A copy with rep movs seems to copy 16 bytes at a time, since speeds for 4,
5, 6 or 7 limb operations are all the same.  The 0.75 cycles/limb would be 3
cycles per 16 byte block.


Instructions in general code have been shown grouped if they can execute
together, which means up to three instructions with no successive
dependencies, and with only the first being a multiple micro-op.

P6 has out-of-order execution, so the groupings are really only showing
dependent paths where some shuffling might allow some latencies to be


"Intel Architecture Optimization Reference Manual", 1999, revision 001 dated
02/99, order number 245127 (order number 730795-001 is in the document too).
Available on-line:

"Intel Architecture Optimization Manual", 1997, order number 242816.  This
is an older document mostly about P5 and not as good as the above.
Available on-line:

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