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User & Date: martin_vahi on 2017-05-12 03:16:17
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2017-05-17 07:34
additional wiki references check-in: 54983c9b9b user: martin_vahi tags: trunk
2017-05-12 03:16
eecg.toronto.edu wiki reference check-in: b9bda3f6f0 user: martin_vahi tags: trunk
2017-05-10 12:47
wiki references check-in: cf7f03865c user: martin_vahi tags: trunk
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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/COMMENTS.txt version [39a0921e6a].

































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The origin:

    http://www.eecg.toronto.edu/parallel/publications.html

    (archival copy: https://archive.is/rZUhA )

    ftp://ftp.cs.toronto.edu/pub/parallel

Many, may be NOT all, of the HTML-files that the wget downloaded, 
were modified so that they reference the files from the 

    ./manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_eduwww.eecg.toronto.edu

in stead of containing URLs to the original FTP-site.

Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/ABSTRACTS version [f912e52af2].





























































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































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---------------------------------------------------------------------
File: Ravi_Stumm_ICPP95.ps.Z

Title: Hierarchical Ring Topologies and the effect of their Bisection
       Bandwidth Constraints

Authors: G. Ravindran and M. Stumm

Where  : Proc. Intl. Conf. on Parallel Processing, pp.I/51-55, 1995

Keywords: Multiprocessor architectures, Interconnection networks,
          Hierarchical rings, Bisection bandwidth

Abstract:

Ring-based hierarchical networks are interesting alternatives to
popular direct networks such as 2D meshes or tori. They allow for
simple router designs, wider communications paths, and faster networks
than their direct network counterparts. However, they have a constant
bisection bandwidth, regardless of system size. In this paper, we
present the results of a simulation study to determine how large
hierarchical ring networks can become before their performance
deteriorates due to their bisection bandwidth constraint. We show that
a system with a maximum of 128 processors can sustain most memory
access behaviors, but that larger systems can be sustained, only if
their bisection bandwidth is increased.

---------------------------------------------------------------------
File: Ravi_Stumm_JIEICE96.ps.Z

Title : A Comparison of Blocking and Non-blocking Packet Switching
        Techniques in Hierarchical Ring Networks

Authors: G. Ravindran and M. Stumm

Where : IEICE Trans. Inf. & Syst., vol. E79-D, No. 8, August 1996

keywords:

Networks, Switching, Wormhole, Virtual Cut-through, Hierarchical Ring Networks,
Slotted Rings

Abstract :

This paper presents the results of a simulation study of blocking and
non-blocking switching for hierarchical ring networks.
The switching techniques include wormhole, virtual cut-through, and
slotted ring.
We conclude that slotted ring network performs better than
the more popular wormhole and virtual cut-through networks.
We also show that the size of the node buffers is an important parameter and
that choosing them too large can hurt performance in some cases.
Slotted rings have the advantage that the choice of buffer size is easier in
that larger than necessary buffers do not hurt performance and hence a single
choice of buffer size performs well for all system configurations.
In contrast, the optimal buffer size for virtual cut-through and wormhole
switching nodes varies depending on the system configuration and the level
in the hierarchy in which the switching node lies.

---------------------------------------------------------------------
File: Zhou_Brecht_SM91.ps.Z

Title: Processor Pool-Based Scheduling for Large-Scale NUMA Multiprocessors

Where: Appears in: Proceedings of  the  1991  ACM  SIGMETRICS  Conference  on
Measurement and Modeling of Computer Systems, May (1991), pp. 133-142.

Authors: Songnian Zhou and Timothy Brecht

Keywords: NUMA, Schedulling, multiprocessor performance

Abstract:
Large-scale  Non-Uniform  Memory  Access  (NUMA)  multiprocessors  are
gaining  increased attention due to their potential for achieving high
performance through the replication of relatively  simple  components.
Because  of  the complexity of such systems, scheduling algorithms for
parallel  applications  are  crucial  in  realizing  the   performance
potential  of  these  systems.  In particular, scheduling methods must
consider the scale of the system, with  the  increased  likelihood  of
creating  bottlenecks,  along  with  the  NUMA  characteristics of the
system, and the benefits to be gained  by  placing  threads  close  to
their code and data.

We propose a class of scheduling algorithms based on processor  pools.
A processor pool is a software construct for organizing and managing a
large number of processors by dividing them into groups called  pools.
The  parallel  threads  of  a  job are run in a single processor pool,
unless there are performance advantages for a  job  to  span  multiple
pools.   Several  jobs may share one pool.  Our simulation experiments
show that processor pool-based scheduling may effectively  reduce  the
average  job  response time.  The performance improvements attained by
using processor pools increase with the  average  parallelism  of  the
jobs, the load level of the system, the differentials in memory access
costs, and the likelihood of having system bottlenecks.  As the system
size   increases,  while  maintaining  the  workload  composition  and
intensity, we observed that processor pools can  be  used  to  provide
significant  performance  improvements.   We  therefore  conclude that
processor pool-based scheduling may  be  an  effective  and  efficient
technique for scalable systems.


---------------------------------------------------------------------
File: Brecht_SEDMS93.ps.Z

Title: On the Importance of Parallel Application Placement
                       in NUMA Multiprocessors

Authors: Timothy Brecht

Where: Proceedings of the Fourth Symposium on Experiences  with
Distributed  and  Multiprocessor  Systems  (SEDMS  IV), San Diego, CA,
September, 1993.

Keywords: NUMA, multiprocessor scheduling, multiprocessor performance  

Abstract:
The thesis of this paper is that scheduling decisions in  large-scale,
shared-memory,  NUMA  (Non-Uniform Memory Access) multiprocessors must
consider not only how many processors, but also  which  processors  to
allocate  to  each  application.   We  call  the  problem of assigning
parallel  processes  of  an  application  to  processors   application
placement.

We explore the importance of  placement  decisions  by  measuring  the
execution  time  of  several  parallel  applications  using  different
placements on a shared-memory NUMA  multiprocessor.   The  results  of
these  experiments  lead  us  to conclude that, as expected, in small-
scale mildly NUMA multiprocessors, placement  decisions  have  only  a
minor affect on the execution time of parallel applications.  However,
the  results  also  show  that  placement  decisions  in   large-scale
multiprocessors  are  critical  and  localization  that  considers the
architectural clusters inherent in these systems  is  essential.   Our
experiments  also  show  that  the  importance  of placement decisions
increases substantially with the size and NUMAness of the  system  and
that  the  placement  of individual processes of an application within
the  subset  of   chosen   processors   also   significantly   impacts
performance.

---------------------------------------------------------------------

File: Kumar_Kulkarni_ICPP91.ps.Z
      (does not contain figures)
Title: Generalized Unimodular Loop Transformations for 
       Distributed Memory Multiprocessors

Authors: K G Kumar*, D Kulkarni+ and A Basu
        Center for Development of Advanced Computing
        2/1 Brunton Road, Bangalore 560 025, India
* Now at IBM TJ Watson, York Town Heights, NY 10598
+ Now at Dept of Computer Science, University of Toronto,
         Toronto, ON M5S 1A4

Where: International Conference of Parallel Processing -91

Keywords: Parallelizing Compilers, Restructuring Transformations, 
          Loop Partitioning, Iteration Spaces, Dependence Vectors.

                           Abstract
In this paper, we present a generalized unimodular loop
transformation as a simple, systematic and elegant method
for partitioning the iteration spaces of nested loops for
execution on distributed memory multiprocessors. We present
a methodology for deriving the transformations that internalize
multiple dependences in a multidimensional iteration space
without resulting in a deadlocking situation. We then
derive the general expression for the bounds of the
transformed loops in terms of the bounds of the original
space and the transformation matrix elements.

-------------------------------------------------------------------

File: Kumar_Kulkarni_ICS92.ps.Z

Title: Deriving Good Transformations for Mapping
       Nested Loops on Hierarchical Parallel Machines
       in Polynomial Time
Authors: K G Kumar*, D Kulkarni+ and A Basu
        Center for Development of Advanced Computing
        2/1 Brunton Road, Bangalore 560 025, India
* IBM TJ Watson, York Town Heights, NY 10598
+ Dept of Computer Science, University of Toronto,
         Toronto, ON M5S 1A4

Where: International Conference on Supercomputing 92

Keywords: Parallelizing Compilers, Restructuring Transformations,
          Loop Partitioning, Iteration Spaces, Dependence Vectors.

We present a computationally efficient method for deriving
the most appropriate transformation and mapping of a nested
loop for a given hierarchical parallel machine. This method
is in the context of our systematic and general theory of
unimodular loop transformations for the problem of iteration
space partitioning \cite{kandk6}. Finding an optimal mapping or
an optimal associated unimodular transformation is NP-complete.
We present a polynomial time method for obtaining a `good'
transformation using a simple parameterized model of the
hierarchical machine. We outline a systematic methodology
for obtaining the most appropriate mapping.

------------------------------------------------------------------- 

File: Li_Tandri_et_ICPP93.ps.Z

Title: LOCALITY AND LOOP SCHEDULING ON NUMA MULTIPROCESSORS

Authors: Hui Li, Sudarsan Tandri Michael Stumm, and Kenneth C. Sevcik

Where: International Conference on Parallel Processing 93

Keywords: NUMA multiprocessors, Locality, Scheduling 

Abstract:
An important issue in the parallel execution of loops is how to
partition and schedule the loops onto the available processors.
While most existing dynamic scheduling algorithms manage load
imbalances well, they fail to take locality into account and
therefore perform poorly on parallel systems with non-uniform
memory access times.  In this paper, we propose a new loop
scheduling algorithm, Locality-based Dynamic Scheduling (LDS),
that exploits locality, and dynamically balances the load.

--------------------------------------------------------------
File: Sandhu_et_al_PPOPP.ps.Z

Title: The shared  regions  approach to software cache coherence on 
       multiprocessors 

Where: Appears in: Proceedings of  the  1993  ACM  SIGPLAN Symposium on
Principles and Pranctice of Parallel Programming, May (1993).

Authors: Harjinder Sandhu, Benjamin Gamsa and Songnian Zhou 

Keywords: NUMA, cache coherence, multiprocessor performance

Abstract: The effective management of caches is critical to the performance of
applications on shared-memory multiprocessors. In this paper,
we discuss a technique for software cache coherence that is
based upon the integration of a program-level abstraction for shared data
with software cache management. The program-level abstraction,
called {\it Shared Regions}, explicitly relates synchronization objects
with the data they protect. Cache coherence algorithms are presented
which use the information provided by shared region primitives, and
ensure that shared regions are always cacheable by the processors accessing
them. Measurements and experiments of the Shared Region approach on a
shared-memory multiprocessor are shown. Comparisons with other software
based coherence strategies, including a user-controlled strategy and an
operating system-based strategy, show that this approach is able to
deliver better performance, with relatively low corresponding overhead
and only a small increase in the programming effort.  Compared to
a compiler-based coherence strategy, the Shared Regions
approach still performs better  than a compiler that can achieve 90\%
accuracy in allowing cacheing, as long as the regions are a few 
hundred bytes or larger, or they are re-used a few times in the cache.

-------------------------------------------------------------------
File: Wilton_Vranesic_SPDP.ps.Z
Title: 
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor

Authors: Steven J.E. Wilton and Zvonko G. Vranesic

To appear in the Fifth IEEE Symposium on Parallel and Distributed Processing,
Irving, Texas, December 1993

Keywords:

Shared-memory multiprocessor, block transfer support

Abstract:

This paper examines how the performance of a shared-memory multiprocessor
can be improved by including hardware support for block transfers.  A system
similar to the Hector multiprocessor developed at the University of Toronto
is used as a base architecture.  It is shown that such hardware support can
improve the performance of initialization code by as much as 50%, but that
the amount of improvement depends on the memory access behavior of the
program and the way in which the operating system issues block transfer
requests.

----------------------------------------------------------------------

File: Sevcik_Zhou_PERF93.ps.Z

Title: Performance Benefits and Limitations of Large NUMA Multiprocessors

Authors: Kenneth C. Sevcik and Songnian Zhou

Where:  appeared in the Proceedings of Performance '93 , Rome, Italy,
  September 27 to October 1, 1993, pp. 183-204, Elsevier Science Publ.

Abstract: Please see the ps file.

----------------------------------------------------------------------
File: Harz_Sevcik_SC93.ps.Z

Title: Hot Spot Analysis in Large Scale Shared Memory Multiprocessors

Authors:  Karim Harzallah and Kenneth C. Sevcik

Where: will appear in the Proceedings of the Supercomputing '93
Conference, November, 1993, Portland, Oregon.

Abstract: Please see the ps file.

-----------------------------------------------------------------------
File: Sevcik_JPE.ps.Z

Title: Application Scheduling and Processor Allocation in 
Multiprogrammed Parallel Processing Systems

Authors:  Kenneth C. Sevcik

Where:  This paper will appear in a special issue of the journal
  "Performance Evaluation" on the performance evaluation of parallel
  systems in late 1993 or early 1994.

Abstract: Please see the ps file.

-----------------------------------------------------------------------
File :   Holliday_Stumm_IEEETC.ps.Z

Title:   Performance Evaluation of Hierarchical Ring-Based Shared 
         Memory Multiprocessors

Authors: Mark Holliday 
         Dept. of Computer Science, Duke University, Durham, NC 27706

         Michael Stumm
         Dept. of Electrical and Computer Engineering
         University of Toronto, Toronto, Canada M5S 1A4 

Date:    November 1992; revised April 1993

Published: Technical Report CS-1992-18, Duke University
         Accepted for publication in IEEE Transactions on Computers

Keywords: communication locality; hierarchical ring-based networks;
         hot spots; large scale parallel systems; memory banks;
         performance evaluation; prefetching; shared memory multiprocessors;
         simulation.

Abstract:

	This paper investigates the performance of word-packet, slotted
	unidirectional ring-based hierarchical direct networks in the
	context of large-scale shared memory multiprocessors.
	Slotted unidirectional rings are attractive because their
	electrical characteristics and simple interfaces allow for fast
	cycle times and large bandwidths.
	For large-scale systems, it is necessary to use multiple rings
	for increased aggregate bandwidth.
	Hierarchies are attractive because the topology ensures unique
	paths between nodes, simple node interfaces and simple inter-ring
	connections.

	To ensure that a realistic region of the design space is examined, 
	the architecture of the network used in the Hector prototype is 
	adopted as the initial design point.
	A simulator of that architecture has been developed and validated with
	measurements from the prototype.
	The system and workload parameterization reflects conditions
	expected in the near future.

	The results of our study show the importance of system balance on 
	performance. Large-scale systems inherently have large
	communication delays for distant accesses, so processor efficiency
	will be low, unless the processors can operate with multiple 
	outstanding transactions using techniques such as prefetching, 
	asynchronous writes and multiple hardware contexts.
	However with multiple outstanding transactions and only one memory
	bank per processing module, memory quickly saturates.
	Memory saturation can be alleviated by having multiple memory
	banks per processing module, but this shifts the bottleneck to the
	ring subsystem.
	While the topology of the ring hierarchy affects performance,
	the ring subsystem will inherently limit the throughput of the system.
	Hence increasing the number of
	outstanding transactions per processor beyond a certain point only
	has a limiting effect on performance, since it causes some of the
	rings to become congested.
	An adaptive maximum number of outstanding
	transactions appears necessary to adjust for the appropriate tradeoff
	between concurrency and contention as the communication locality 
	changes. We show the relationships between processor, ring and memory 
	speeds, and their effects on performance.
	Using block transfers for prefetching seems unlikely to be advantageous
	in that the improvement in the cache hit ratio needed to compensate for
	the increased network utilization is substantial.


-------------------------------------------------------------------------
File : Curran_Stumm_CS.ps.Z

Title:     A Comparison of basic CPU Scheduling Algorithms for 
           Multiprocessor Unix

Authors:   Stephen Curran  and  Michael Stumm
           Department of Electrical and Computer Engineering
           University of Toronto, Toronto, Canada M5S 1A4

Published: Computer Systems, 3(4), Oct., 1990, pp. 551--579.

Abstract:
	In this paper, we present the results of a simulation study
	comparing three basic algorithms that schedule independent tasks in 
	multiprocessor versions of Unix.
	Two of these algorithms, namely Central Queue and Initial Placement,
	are obvious extensions to the standard uniprocessor scheduling 
	algorithm and are in use in a number of multiprocessor systems.
	A third algorithm, Take, is a variation on Initial Placement,
	where processors are allowed to raid the task queues of the other
	processors.
	Our simulation results show the difference between the
	performance of the three algorithms to be small when
	scheduling a typical Unix workload running on a small, bus-based,
	shared memory multiprocessor.
	They also show that the Take algorithm performs best for those
	multiprocessors on which tasks incur overhead each time they migrate.
	In particular, the Take algorithm appears to be more stable
	than the other two algorithms under extreme conditions.


-----------------------------------------------------------------------

File: Stumm_Unrau_Krieger_USENIX92.ps.Z

Title:  HIERARCHICAL CLUSTERING: A STRUCTURE FOR SCALABLE MULTIPROCESSOR
          OPERATING SYSTEM DESIGN

Authors: Michael Stumm, Ron Unrau, and Orran Krieger 

Where:  Extended version of Clustering Micro-Kernels for Scalability,
        Proc.\ of the Usenix Workshop on Micro-Kernels and
        Other Kernel Architectures, April, 1992.

Abstract: Please see the ps file.

----------------------------------------------------------------------

File: Stumm_Vranesic_White_IPPS93.ps.Z

Title: EXPERIENCE WITH THE HECTOR MULTIPROCESSOR 

Authors: Michael Stumm, Zvonko Vranesic, Ron White

Where:  Extended version of paper with same title
        in Proc.\ Intl.\ Parallel Processing Symposium
        Parallel Systems Fair, 1993, pp.\ 9--16.

Abstract: Please see the ps file.

----------------------------------------------------------------------

File: Krieger_Stumm_Unrau_USENIX92.ps.Z

Title: The Alloc Stream Facility: A redesign of application-level
Stream I/O 

Authors: O. Krieger, M. Stumm, and R. Unrau

Where: Extended version of
``Exploiting the advantages of mapped files for stream I/O''
in Proc.\ of the Winter 1992 Usenix Conference, January, 1992.

Abstract:
This paper describes the design and implementation of a new
application level I/O facility, called the Alloc Stream Facility.
The Alloc Stream Facility has several key advantages.  First,
performance is substantially improved as a result of a)~the
structure of the facility that allows it to take advantage of
system specific features like mapped files, and b)~a reduction in
data copying and the number of I/O system calls.  Second, the
facility is designed for multi-threaded applications running on
multiprocessors and allows for a high degree of concurrency.
Finally, the facility can support a variety of I/O interfaces,
including stdio, emulated Unix I/O, ASI, and C++ streams, in a
way that allows applications to freely intermix calls to the
different interfaces, resulting in improved code reusability.

We show that on several Unix workstation platforms the
performance of Unix applications using the Alloc Stream Facility
can be substantially better that when the applications use the
original I/O facilities.


----------------------------------------------------------------------

File: Krieger_Stumm_DAGS93.ps.Z

Title: HFS: A Flexible File System for large-scale Multiprocessors 

Authors: Orran Krieger and Michael Stumm

Where: Proceedings of the 1993 DAGS/PC Symposium

Abstract:
The {H{\sc urricane}} File System (HFS) is a new file system
  being developed for large-scale shared memory multiprocessors with
  distributed disks. The main goal of this file system is scalability; that is,
  the file system is designed to handle demands that are expected to grow
  linearly with the number of processors in the system. To achieve this goal,
  HFS is designed using a new structuring technique called Hierarchical
  Clustering. HFS is also designed to be flexible in supporting a variety of
  policies for managing file data and for managing file system state. This
  flexibility is necessary to support in a scalable fashion the diverse
  workloads we expect for a multiprocessor file system.


----------------------------------------------------------------------

File: Krieger_etal_ICPP93.ps.Z

Title: A fair fast scalable reader-writer lock 

Authors: O. Krieger, M. Stumm, R. Unrau, and J. Hanna,

Where: Proc. Intl. Conf. on Parallel Processing, 1993.

Abstract:
A reader-writer lock allows either multiple readers to inspect
  shared data or a single writer exclusive access to that data.  On
  shared memory multiprocessors, the cost of acquiring and
  releasing these locks can have a large impact on the performance
  of parallel applications.  Other researchers have shown how to
  implement scalable locks, that is, locks that can become
  contended without resulting in memory or interconnection network
  contention.  This paper describes a new algorithm for a
  reader-writer lock that, while being scalable in the contended
  case, has a low overhead in the uncontended case.  This is
  important because most parallel applications are written so that
  locks are typically uncontended.  The only atomic operation
  required by this algorithm is fetch_and_store and hence
  it can be used on most current multiprocessor systems.
  Experimental results are provided.

----------------------------------------------------------------------

File: Kulkarni_Stumm_Tutorial.ps.Z

Title: Loop and Data Transformations: A tutorial

Authors: Dattatraya Kulkarni and Michael Stumm

Where: Internal document, a tutorial guide.

Abstract:
Hierarchically structured machines appear to be becoming the
dominant parallel computing structure. These systems have
non-uniform access times. We address the problem of restructuring
a possibly sequential program to execute efficiently on such
parallel machines. This restructuring involves transforming and
partitioning the loop structures and the data to so as to improve
{\it parallelism}, {\it static} and {\it dynamic locality}, and {\it
load balance}.
The objective of this paper is to present previous and ongoing work
on loop and data transformations and motivate a {\it unified} framework to
restructuring of a sequence of loops and data so as to execute efficiently on
parallel machines with several levels of hierarchy.

----------------------------------------------------------------------


File: Baru_Zilio_PADS93.ps.Z

Title: Data reorganization in parallel database systems

Author: Chaitanya Baru & Daniel C. Zilio

Where : Proc. of the IEEE Workshop on Advances in Parallel and
Distributed Systems}, Princeton, NJ, pp.102-107, Oct.  1993.

Abstract: Parallel database systems are suitable for use in
applications with high capacity and high performance and availability
requirements.  The trend in such systems is to provide efficient
on-line capability for performing various system administration
functions such as, index creation and maintenance, backup/restore,
reorganization, and gathering of statistics.  For some of these
functions, the on-line capability can be efficiently supported by the
use of ``incremental algorithms", i.e., algorithms that achieve the
function in several, relatively small (i.e., less time-consuming)
steps, rather than in a single, large step.  Incremental algorithms
ensure that only small parts of the database become inaccessible for
short durations as opposed to non-incremental algorithms which may
lock large portions of the database or the entire database for a
longer duration.  In this paper, we discuss issues in providing
concurrent data reorganization capability using incremental algorithms
in parallel database systems.


----------------------------------------------------------------------

File: Kulkarni_Stumm_292.ps.Z

Title: Computational Alignment:
A new, unified program transformation for local and global optimization

Authors: Dattatraya Kulkarni and Michael Stumm

Where: CSRI Tech report 292, ISSN 0834-1648

Abstract:
{\small {\em Computational Alignment} is a new class of program
transformations suitable for both local and global optimization.
Computational Alignment transforms all of the computations of a
{\em portion} of the loop body in order to align them to other
computations either in the same loop or in another loop. It
extends along a new dimension and is significantly more powerful
than linear transformations because $i)$
it can transform subsets of dependences and references;
$ii)$ it is sensitive to the location of data in that it can move
the computation relative to data; $iii)$ it applies to imperfect
loop nests; and $iv)$ it is the first loop transformation that
can change {\it access vectors}. Linear transformations are just a
special case of Computational Alignment.
Computational Alignment is highly suitable for global
optimization because it can transform given loops to access data
in similar ways. Two important subclasses of Computational
Alignment are presented as well, namely, {\em Freeing} and {\em
Isomerizing} Computational Alignment.}

-------------------------------------------------------------
File: Brecht_PhD_303.ps.Z

Title: Multiprogrammed Parallel Application Scheduling in NUMA Multiprocessors

Authors: Timothy B. Brecht

Where: Ph.D. Dissertation - CSRI Technical Report CSRI-303

Abstract:

          The   invention,   acceptance,    and    proliferation    of
     multiprocessors  are  primarily a result of the quest to increase
     computer system performance.   The  most  promising  features  of
     multiprocessors are their potential to solve problems faster than
     previously possible and to solve larger problems than  previously
     possible.    Large-scale  multiprocessors  offer  the  additional
     advantage of being able to execute multiple parallel applications
     simultaneously.

          The execution time of a  parallel  application  is  directly
     related  to  the  number  of  processors  it is allocated and, in
     shared-memory   non-uniform    memory    access    time    (NUMA)
     multiprocessors,  which processors it is allocated.  As a result,
     efficient and effective scheduling becomes  critical  to  overall
     system  performance.   In fact, it is likely to be a contributing
     factor in  ultimately  determining  the  success  or  failure  of
     shared-memory NUMA multiprocessors.

          The subjects  of  this  dissertation  are  the  problems  of
     processor  allocation  and  application placement.  The processor
     allocation problem involves determining the number of  processors
     to  allocate to each of several simultaneously executing parallel
     applications and possibly dynamically adjusting those allocations
     to  improve  overall  system performance.  The performance metric
     used is mean response time.   We  show  that  by  differentiating
     between  applications  based on the amount of remaining work they
     have to execute, performance can be improved significantly.  Then
     we  propose  techniques  for estimating an application's expected
     remaining work along with policies for using these  estimates  to
     make  improved  processor  allocation decisions.  An experimental
     evaluation demonstrates the promise of this approach.

          The placement problem involves determining which of the many
     processors  to  assign  to  each  application.  Using experiments
     conducted on a representative  system,  we  demonstrate  that  in
     large-scale  NUMA  multiprocessors the execution time of parallel
     applications is significantly affected by the  placement  of  the
     application.  This motivates the need for new techniques designed
     explicitly  for  NUMA  multiprocessors.   We  introduce  such   a
     technique,   called  processor  pool-based  scheduling,  that  is
     designed to  localize  the  execution  of  parallel  applications
     within  a  NUMA  architecture  and  to isolate different parallel
     applications from each other.  An experimental evaluation of this
     scheduling  method  shows  that  it  can be used to significantly
     reduce mean response time over methods that do not  consider  the
     placement of parallel applications.

-------------------------------------------------------------------
File: Gamsa_MASc.ps.Z

Title: Region-Oriented Main Memory Management
       in Shared-Memory NUMA Multiprocessors


Authors: Benjamin Gamsa

Where: M.Sc. Thesis

Abstract:

     In Non-Uniform Memory Access  time  (NUMA)  multiprocessors,
     distribution of the memory modules facilitates architectural
     scaling,  but creates complications for the programmers  who
     must  be  concerned  with the physical distribution of their
     data in order to obtain good performance.

     In order to reduce the impact of remote  accesses,  in  this
     thesis  we  propose  that  data  be  partitioned into Shared
     Regions that reflect the  granularity  of  data  sharing  in
     programs, and that special synchronization calls be added to
     enforce proper ordering of accesses to the  shared  data  as
     well  as to manage replication and consistency transparently
     to the programmer.

     Results   from   measurements   on   a   16-processor   NUMA
     multiprocessor  and from a model of the system indicate that
     the Shared Regions approach is successful in  obtaining  the
     necessary  locality critical to performance, while incurring
     only minimal overhead.  Data distribution methods  are  also
     observed  to have a significant impact on the performance of
     the  system,  especially  in  the   larger   multiprocessors
     modeled.

-------------------------------------------------------------------

File: Unrau_PhD.ps.Z

Title: Scalable Memory Management through Hierarchical 
       Symmetric Multiprocessing

Authors: Ronald C. Unrau

Where: Ph.D. Disseration

Abstract:

     This dissertation examines scalability issues in  the  design  of
     operating systems for large-scale, shared-memory multiprocessors.
     In particular, the thesis focuses on structuring issues  as  they
     relate to memory management.

     From a set of simple, well-known  queuing  network  formulas,  we
     derive  a  set  of properties that describe sufficient conditions
     for an operating system to scale. From these properties we  first
     develop  a  set of guidelines for designing scalable systems, and
     then develop  a  new  structuring  philosophy  for  shared-memory
     multiprocessor  operating  systems, called Hierarchical Symmetric
     Multiprocessing (HSM).

     HSM  manages  the  system  resources  in  clusters,  using  tight
     coupling  within  a  cluster, and loose coupling across clusters.
     Distributed systems principles are applied  by  distributing  and
     replicating   system   services  and  data  objects  to  increase
     locality,  increase  concurrency,  and   to   avoid   centralized
     bottlenecks,  thus  making  the  system scalable.  However, tight
     coupling is used within a cluster, so the  system  performs  well
     for  local  interactions.  HSM maximizes locality which is key to
     good performance in large systems, and systems based on  HSM  can
     easily  be  adapted  to  different  hardware  configurations  and
     architectures by changing the size of the clusters.  Finally, HSM
     leads  to a modular system composed from easy-to-design and hence
     efficient building blocks.

     Memory  management  is  a  particularly  challenging  service  to
     implement  within  the HSM framework, because it must provide the
     applications with an integrated and coherent  view  of  a  single
     system,  while  distributing and replicating services in order to
     fully exploit the hardware potential. We describe in  detail  the
     implementation  of an HSM structured memory management subsystem,
     and evaluate the performance of our implementation on  Hector,  a
     prototype scalable shared memory multiprocessor.

-------------------------------------------------------------------

File: Wu_MASc.ps.Z

Title: Processor Scheduling in Multiprogrammed Shared Memory 
       NUMA Multiprocessors

Authors: Chee-Shong Wu

Where: M.Sc. Thesis

Abstract:

     In a multiprogrammed multiprocessor, the scheduler  is  not  only
     responsible for deciding when to activate an application and when
     to suspend it, but is also responsible for determining  how  many
     processors  to  allocate  to each application. In a scalable Non-
     Uniform Memory Access  (NUMA)  multiprocessor,  it  must  further
     resolve  the  problem  of which processor(s) to allocate to which
     application since the memory reference times are not the same for
     all processor-memory pairs.

     In this thesis, we study  the  problem  of  how  to  characterize
     parallel   applications  and  how  to  apply  this  knowledge  in
     scheduling for NUMA systems.  We also study  the  performance  of
     several  scheduling  algorithms  in  an  NUMA  environment. These
     algorithms differ in the frequency of reallocations.  We  propose
     two  policies,  the  Static policy and the Immediate Start Static
     policy, that  utilize  application  characteristics  when  making
     scheduling  decisions.   The performance of these two policies is
     compared  with  that  of  the  Dynamic   policy,   on   an   NUMA
     multiprocessor, Hector.

---------------------------------------------------------------------
File: Parsons_Sevcik_IPPS95.ps.Z

Title: Multiprocessor Scheduling for High-Variability Service Time
       Distributions
 
Where: IPPS '95 Workshop on Job Scheduling Strategies for Parallel Processing
  reprinted in Springer-Verlag Lecture Notes in Computer Science, Vol 949,
  pages 127--145.

Authors: Eric W. Parsons and Kenneth C. Sevcik 

Keywords: Scheduling, multiprocessor performance

Abstract:
  Many disciplines have been proposed for scheduling and processor
  allocation in multiprogrammed multiprocessors for parallel processing.
  These have been, for the most part, designed and evaluated for workloads
  having relatively low variability in service demand.  But with reports
  that variability in service demands at high performance computing centers
  can actually be quite high, these disciplines must be reevaluated.  In
  this paper, we examine the performance of two well-known static
  scheduling disciplines, and propose preemptive versions of these that
  offer much better mean response times when the variability in service
  demand is high.  We argue that, in systems in which dynamic
  repartitioning in applications is expensive or impossible, these
  preemptive disciplines are well suited for handling high variability in
  service demand.

---------------------------------------------------------------------
File:  Okrieg_PhD.ps.Z

Title: HFS: A flexible file system for shared-memory multiprocessors 

Where: PhD Dissertation, Department of Electrical and Computer Engineering,
University of Toronto

Authors: Orran Krieger 

Keywords: File System, I/O, Hurricane, Hector NUMA multiprocessor

Abstract:

  The Hurricane File System (HFS) is designed for large-scale, shared-memory
  multiprocessors.  Its architecture is based on the principle that a
  file system must support a wide variety of file structures, file
  system policies and I/O interfaces to maximize performance
  for a wide variety of applications.  HFS uses a novel, object-oriented
  building-block approach to provide the flexibility needed to support
  this variety of file structures, policies, and I/O interfaces.  File
  structures can be defined in HFS that optimize for sequential or
  random access, read-only, write-only or read/write access, sparse or
  dense data, large or small file sizes, and different degrees of
  application concurrency.  Policies that can be defined on a per-file
  or per-open instance basis include locking policies, prefetching
  policies, compression/decompression policies and file cache management
  policies.  In contrast, most existing file systems have been designed
  to support a single file structure and a small set of policies.

  We have implemented large portions of HFS as part of the Hurricane operating
  system running on the \hec\ shared-memory multiprocessor.  We
  demonstrate that the flexibility of HFS comes with little processing
  or I/O overhead.  Also, we show that HFS is able to deliver the full
  I/O bandwidth of the disks on our system to the applications.

---------------------------------------------------------------------
File: Vranesic_etal_IEEEC.ps.Z 

Title: Hector -- A hierarchically structured shared memory multiprocessor

Where: IEEE Computer, 24(1): 72-80, January, 1991.

Authors: Z. Vranesic, M. Stumm, D. Lewis and R. White 

Keywords: Shared memory multiprocessors, slotted rings, NUMA, Scalability. 

Abstract: Please see the ps file.

---------------------------------------------------------------------
File: Kulkarni_etal_317.ps.Z 

Title: A Generalized Theory of Linear Loop Transformations

Where: CSRI Tech Report 317

Authors: D. Kulkarni, M. Stumm, R. Unrau 

Keywords: Computational Alignment, Computation Decomposition,
Linear loop transformations, SPMD code generation.

Abstract: In this paper we present a new theory of linear loop transformations
called {\em Computation Decomposition and Alignment\/} (CDA). A CDA
transformation has two components: {\em Computation Decomposition\/}
first decomposes the computations in the loop into computations
of finer granularity, from iterations to instances of subexpressions.
{\em Computation Alignment\/} subsequently, linearly transforms each
of these sets of computations, possibly by using a
different transformation for each set.  This framework subsumes all
existing linear transformation frameworks in that it reduces to a
conventional linear loop transformation when the smallest granularity
is an iteration, and it reduces to some of the more recently extended
frameworks when the smallest granularity is a statement instance.
The possibility  of being able to align computations at arbitrary
granularities adds a new dimensions to performance optimization
on high performance computing platforms.

We describe Computation Decomposition and Alignment and provide
examples of CDA transformations. We present some heuristics to
derive appropriate CDA transformations, given a desired optimization
objective. We present the results of experiments run on
the KSR1 multiprocessor and various RS6000 and
Sparc platforms that demonstrate that CDA can result in substantial
performance improvements.

---------------------------------------------------------------------
File: Kulkarni_Stumm_ACJ95.ps.Z 

Title: Linear Loop Transformations in Optimizing Compilers for Parallel Machines

Where: To appear in the Australian Computer Journal

Authors: D. Kulkarni, M. Stumm 

Keywords:  Linear loop transformations

Abstract: We present the linear loop transformation framework which is the formal
basis for state of the art optimization techniques in restructuring
compilers for parallel machines. The framework unifies most existing
transformations and provides a systematic set of code generation
techniques for arbitrary compound loop transformations. The algebraic
representation of the loop structure and its transformation give
way to quantitative techniques for optimizing performance on parallel
machines. We discuss in detail the techniques for generating
the transformed loop and deriving the desired linear transformation.

---------------------------------------------------------------------
File: Manjikian_Abdelrahman_315.ps.Z 

Title: Fusion of Loops for Parallelism and Locality

Where: CSRI Tech Report 315

Authors: N. Manjikian and T. Abdelrahaman

Keywords:  Loop fusion, cache performance, locality, NUMA

Abstract: Loop fusion improves data locality and reduces synchronization in
data-parallel applications. However, loop fusion is not always
legal. Even when legal, fusion may introduce loop-carried dependences
which reduce parallelism. In addition, performance losses result from
cache conflicts in fused loops. We present new, systematic techniques
which: (1) allow fusion of loop nests in the presence of
fusion-preventing dependences, (2) allow parallel execution of fused
loops with minimal synchronization, and (3) eliminate cache conflicts
in fused loops. We evaluate our techniques on a 56-processor KSR2
multiprocessor, and show performance improvements of up to 20% for
representative loop nest sequences. The results also indicate a
performance tradeoff as more processors are used, suggesting a careful
evaluation of the profitability of fusion.

 
<!--------------------------------------------------------------------->
<HR>
<A NAME="Kulkarni_Stumm_LCR95">.</A>
<HR>

<B>Title:</B> <A HREF="ftp://ftp.cs.toronto.edu/pub/parallel/Kulkarni_Stumm_LCR95.ps.Z">CDA Loop Transformations</A> 
 <P>
<B>Authors:</B> Dattatraya Kulkarni and Michael Stumm 
 <P>
<B>Where:</B> Proceedings of the Third workshop on languages, compilers and run-
time systems
  for scalable computers}, Troy, NY, May 1995, Kluwer Academic. 
 <P>
<B>Abstract:</B>
 <P>

In this paper we present a new loop transformation technique
called {\em Computation Decomposition and Alignment\/} (CDA).
{\em Computation Decomposition\/}
first decomposes the iteration space into finer computation spaces.
{\em Computation  Alignment\/} subsequently, linearly transforms each
computation space independently.
CDA is a general framework in that
linear transformations and its recent extensions are just special cases of CDA.
CDA's fine grained loop restructuring can incur considerable
computational effort, but can exploit optimization
opportunities that earlier frameworks cannot. We present four
optimization contexts in which CDA can be useful. Our
initial experiments demonstrate that CDA adds a new dimension to
performance optimization.

<!--------------------------------------------------------------------->
<HR>
<A NAME="Kulkarni_Stumm_EuroPar95">.</A>
<HR>

<B>Title:</B> <A HREF="ftp://ftp.cs.toronto.edu/pub/parallel/Kulkarni_Stumm_EuroPar95.ps.Z">Implementing Flexible Computation Rules with
Subexpression-level Loop Transformations</A> 
 <P>
<B>Authors:</B> Dattatraya Kulkarni, Michael Stumm  and Ronald C. Unrau
 <P>
<B>Where:</B>Proceedings of the Euro-Par95, Stockholm, Aug 28-31, 1995. 
 <P>
<B>Abstract:</B>
 <P>

  Computation Decomposition and Alignment (CDA) is a new loop transformation
  framework that extends the linear loop transformation framework and
the more recently proposed
  Computation Alignment frameworks by linearly transforming
  computations at the granularity of subexpressions.
  It can be applied to achieve a number of optimization objectives,
  including the removal of data alignment constraints, the elimination
  of ownership tests, the reduction of cache conflicts, and
improvements in data access locality.

  In this paper we show how CDA can be used to effectively implement
  flexible computation rules with the objective of minimizing
  communication and, whenever possible, eliminating intrinsics that
  test whether computations need to be executed or not.
  We describe CDA, show how it can be used to implement flexible
  computation rules, and present an algorithm for deriving appropriate
  CDA transformations.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Unrau_etal_EuroPar95">.</A>
<HR>

<B>Title:</B> <A HREF="ftp://ftp.cs.toronto.edu/pub/parallel/Unrau_etal_EuroPar95.ps.Z">On the Scalability of Demand-Driven Parallel Systems </A> 
 <P>
<B>Authors:</B> Ronald C. Unrau and Michael Stumm and Orran Krieger 
 <P>
<B>Where:</B>Proceedings of the Euro-Par95, Stockholm, Aug 28-31, 1995. 
 <P>
<B>Abstract:</B>
 <P>

Demand-driven systems follow the model where customers enter the system,
request some service, and then depart.
Examples are databases, transaction processing systems and operating systems,
which form the system software layer between the applications and the hardware.
Achieving scalability at the system software layer is critical
for the scalability of the system as a whole, and yet this layer
has largely been ignored.

In this paper, we characterize the scalability of the system software layer
of demand-driven parallel systems 
based on fundamental metrics of quantitative system performance analysis.
We develop a set of sufficient conditions so that
if a system satisfies these conditions, then the system is scalable.
We further argue that in practice these conditions are also necessary.
In the remainder of the paper, we use the necessary and sufficient conditions 
to develop a set of practical design guidelines, to study the effect of
application workloads, and to examine the scalability behavior of a system with
only a limited number of processors.

<!--------------------------------------------------------------------->
<HR>
<A NAME="Parsons_etal_IWOOS95">.</A>
<HR>

<B>Title:</B> <A HREF="ftp://ftp.cs.toronto.edu/pub/parallel/Parsons_etal_IWOOS95.ps.Z">(De-)Clustering Objects for Multiprocessor System Software </A> 
 <P>
<B>Authors:</B> Eric Parsons, Ben Gamsa, Orran Krieger, Michael Stumm
<P>
<B>Where:</B> IWOOS95 (Fourth International Workshop on Object Orientation in Operating Systems 95)  
<P>
<B>Abstract:</B>
 <P>

  Designing system software for large-scale shared-memory multiprocessors
  is challenging because of the level of performance demanded by the
  application workload and the distributed nature of the system.  Adopting
  an object-oriented approach for our system, we have developed a framework
  for de-clustering objects, where each object may migrate, replicate, and
  distribute all or part of its data across the system memory using the
  policies that will best meet the locality requirements for that data.  The
  mechanism for object invocation hides the internal structure of an
  object, allowing a request to be made directly to the most suitable part
  of the object on a per-processor basis without any knowledge of how the
  object is de-clustered.  Method invocation is very efficient, both within
  and across address spaces, involving no remote memory accesses in the
  common case.  We describe the design and implementation of this framework
  in Tornado, our multiprocessor operating system.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Ben_etal_OOPSLAW94">.</A>
<HR>

<B>Title:</B> <A HREF="ftp://ftp.cs.toronto.edu/pub/parallel/Ben_etal_OOPSLAW94.ps.Z">The Importance of Performance-Oriented Flexibility in
System Software for Large-Scale Shared-Memory Multiprocessors
 </A> 
 <P>
<B>Authors:</B> 
Orran Krieger, Ben Gamsa, Karen Reid, Paul Lu, Eric Parsons and Michael Stumm
<P>
<B>Where:</B> 
OOPSLA Workshop on Flexible System Software. October 1994.
<P>
<B>Abstract:</B>
 <P>
See paper for abstract.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Orran_etal_SPDPW95">.</A>
<HR>

<B>Title:</B> <A HREF="ftp://ftp.cs.toronto.edu/pub/parallel/Orran_etal_SPDPW95.ps.Z">
 Exploiting Mapped Files for Parallel I/O
</A> 
 <P>
<B>Authors:</B> 
Orran Krieger, Karen Reid and Michael Stumm
<P>
<B>Where:</B> 
SPDP Workshop on Modeling and Specification of I/O (MSIO), October 1995

<P>
<B>Abstract:</B>
 <P>
  Harnessing the full I/O capabilities of a large-scale multiprocessor is
  difficult and requires a great deal of cooperation between the
  application programmer, the compiler and the operating (/file) system.
  Hence, the parallel I/O interface used by the application to communicate
  with the system is crucial in achieving good performance.  We present a
  set of properties we believe that a good I/O interface should have and
  consider current parallel I/O interfaces from the perspective of these
  properties.  We describe the advantages and disadvantages of mapped-file
  I/O and argue that if properly implemented it can be a good basis for a
  parallel I/O interface that can fulfill the suggested properties.  To
  demonstrate that such an implementation is feasible, we describe
  methodology used in our previous work on the Hurricane operating system
  and in our current work on the Tornado operating system to implement
  mapped files.












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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Gamsa_etal_ICPP94.ps.Z version [37e7a07dbe].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Harz_Sevcik_SC93.ps.Z version [cdaa8a7875].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Holliday_Stumm_IEEETC.ps.Z version [9eac90ad8c].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Krieger_Stumm_DAGS93.ps.Z version [a8661224c1].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Krieger_Stumm_Unrau_USENIX92.ps.Z version [a50dc80555].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Krieger_etal_ICPP93.ps.Z version [a93baad145].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Krieger_etal_IEEEComp94.ps.Z version [ce1ab5a5a0].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kulkarni_Stumm_292.ps.Z version [d4c59465ba].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kulkarni_Stumm_ACJ95.ps.Z version [6c3b324030].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kulkarni_Stumm_CDA.ps.Z version [e3cb470a06].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kulkarni_Stumm_LCR95.ps.Z version [162ba80033].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kulkarni_Stumm_Tutorial.ps.Z version [6828d2a140].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kulkarni_Stumm_Unrau_EuroPar95.ps.Z version [9dac4bd560].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kulkarni_etal_317.ps.Z version [34eccfe707].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Kumar_Kulkarni_ICPP91.ps.Z version [3940104ad0].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Li_Tandri_et.ps.Z version [0386572be6].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Sevcik_Zhou_PERF93.ps.Z version [32a44a59ed].

cannot compute difference between binary files

Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Stumm_Unrau_Krieger_USENIX92.ps.Z version [0eb56da9b7].

cannot compute difference between binary files

Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Stumm_Vranesic_White_IPPS93.ps.Z version [3e88aab020].

cannot compute difference between binary files

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[2089955127].


























































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































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/IdrawDict 51 dict def
IdrawDict begin

/reencodeISO {
dup dup findfont dup length dict begin
{ 1 index /FID ne { def }{ pop pop } ifelse } forall
/Encoding ISOLatin1Encoding def
currentdict end definefont
} def

/ISOLatin1Encoding [
/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef
/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef
/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef
/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef
/space/exclam/quotedbl/numbersign/dollar/percent/ampersand/quoteright
/parenleft/parenright/asterisk/plus/comma/minus/period/slash
/zero/one/two/three/four/five/six/seven/eight/nine/colon/semicolon
/less/equal/greater/question/at/A/B/C/D/E/F/G/H/I/J/K/L/M/N
/O/P/Q/R/S/T/U/V/W/X/Y/Z/bracketleft/backslash/bracketright
/asciicircum/underscore/quoteleft/a/b/c/d/e/f/g/h/i/j/k/l/m
/n/o/p/q/r/s/t/u/v/w/x/y/z/braceleft/bar/braceright/asciitilde
/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef
/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef
/.notdef/dotlessi/grave/acute/circumflex/tilde/macron/breve
/dotaccent/dieresis/.notdef/ring/cedilla/.notdef/hungarumlaut
/ogonek/caron/space/exclamdown/cent/sterling/currency/yen/brokenbar
/section/dieresis/copyright/ordfeminine/guillemotleft/logicalnot
/hyphen/registered/macron/degree/plusminus/twosuperior/threesuperior
/acute/mu/paragraph/periodcentered/cedilla/onesuperior/ordmasculine
/guillemotright/onequarter/onehalf/threequarters/questiondown
/Agrave/Aacute/Acircumflex/Atilde/Adieresis/Aring/AE/Ccedilla
/Egrave/Eacute/Ecircumflex/Edieresis/Igrave/Iacute/Icircumflex
/Idieresis/Eth/Ntilde/Ograve/Oacute/Ocircumflex/Otilde/Odieresis
/multiply/Oslash/Ugrave/Uacute/Ucircumflex/Udieresis/Yacute
/Thorn/germandbls/agrave/aacute/acircumflex/atilde/adieresis
/aring/ae/ccedilla/egrave/eacute/ecircumflex/edieresis/igrave
/iacute/icircumflex/idieresis/eth/ntilde/ograve/oacute/ocircumflex
/otilde/odieresis/divide/oslash/ugrave/uacute/ucircumflex/udieresis
/yacute/thorn/ydieresis
] def
/Times-Roman reencodeISO def

/none null def
/numGraphicParameters 17 def
/stringLimit 65535 def

/Begin {
save
numGraphicParameters dict begin
} def

/End {
end
restore
} def

/SetB {
dup type /nulltype eq {
pop
false /brushRightArrow idef
false /brushLeftArrow idef
true /brushNone idef
} {
/brushDashOffset idef
/brushDashArray idef
0 ne /brushRightArrow idef
0 ne /brushLeftArrow idef
/brushWidth idef
false /brushNone idef
} ifelse
} def

/SetCFg {
/fgblue idef
/fggreen idef
/fgred idef
} def

/SetCBg {
/bgblue idef
/bggreen idef
/bgred idef
} def

/SetF {
/printSize idef
/printFont idef
} def

/SetP {
dup type /nulltype eq {
pop true /patternNone idef
} {
dup -1 eq {
/patternGrayLevel idef
/patternString idef
} {
/patternGrayLevel idef
} ifelse
false /patternNone idef
} ifelse
} def

/BSpl {
0 begin
storexyn
newpath
n 1 gt {
0 0 0 0 0 0 1 1 true subspline
n 2 gt {
0 0 0 0 1 1 2 2 false subspline
1 1 n 3 sub {
/i exch def
i 1 sub dup i dup i 1 add dup i 2 add dup false subspline
} for
n 3 sub dup n 2 sub dup n 1 sub dup 2 copy false subspline
} if
n 2 sub dup n 1 sub dup 2 copy 2 copy false subspline
patternNone not brushLeftArrow not brushRightArrow not and and { ifill } if
brushNone not { istroke } if
0 0 1 1 leftarrow
n 2 sub dup n 1 sub dup rightarrow
} if
end
} dup 0 4 dict put def

/Circ {
newpath
0 360 arc
patternNone not { ifill } if
brushNone not { istroke } if
} def

/CBSpl {
0 begin
dup 2 gt {
storexyn
newpath
n 1 sub dup 0 0 1 1 2 2 true subspline
1 1 n 3 sub {
/i exch def
i 1 sub dup i dup i 1 add dup i 2 add dup false subspline
} for
n 3 sub dup n 2 sub dup n 1 sub dup 0 0 false subspline
n 2 sub dup n 1 sub dup 0 0 1 1 false subspline
patternNone not { ifill } if
brushNone not { istroke } if
} {
Poly
} ifelse
end
} dup 0 4 dict put def

/Elli {
0 begin
newpath
4 2 roll
translate
scale
0 0 1 0 360 arc
patternNone not { ifill } if
brushNone not { istroke } if
end
} dup 0 1 dict put def

/Line {
0 begin
2 storexyn
newpath
x 0 get y 0 get moveto
x 1 get y 1 get lineto
brushNone not { istroke } if
0 0 1 1 leftarrow
0 0 1 1 rightarrow
end
} dup 0 4 dict put def

/MLine {
0 begin
storexyn
newpath
n 1 gt {
x 0 get y 0 get moveto
1 1 n 1 sub {
/i exch def
x i get y i get lineto
} for
patternNone not brushLeftArrow not brushRightArrow not and and { ifill } if
brushNone not { istroke } if
0 0 1 1 leftarrow
n 2 sub dup n 1 sub dup rightarrow
} if
end
} dup 0 4 dict put def

/Poly {
3 1 roll
newpath
moveto
-1 add
{ lineto } repeat
closepath
patternNone not { ifill } if
brushNone not { istroke } if
} def

/Rect {
0 begin
/t exch def
/r exch def
/b exch def
/l exch def
newpath
l b moveto
l t lineto
r t lineto
r b lineto
closepath
patternNone not { ifill } if
brushNone not { istroke } if
end
} dup 0 4 dict put def

/Text {
ishow
} def

/idef {
dup where { pop pop pop } { exch def } ifelse
} def

/ifill {
0 begin
gsave
patternGrayLevel -1 ne {
fgred bgred fgred sub patternGrayLevel mul add
fggreen bggreen fggreen sub patternGrayLevel mul add
fgblue bgblue fgblue sub patternGrayLevel mul add setrgbcolor
eofill
} {
eoclip
originalCTM setmatrix
pathbbox /t exch def /r exch def /b exch def /l exch def
/w r l sub ceiling cvi def
/h t b sub ceiling cvi def
/imageByteWidth w 8 div ceiling cvi def
/imageHeight h def
bgred bggreen bgblue setrgbcolor
eofill
fgred fggreen fgblue setrgbcolor
w 0 gt h 0 gt and {
l b translate w h scale
w h true [w 0 0 h neg 0 h] { patternproc } imagemask
} if
} ifelse
grestore
end
} dup 0 8 dict put def

/istroke {
gsave
brushDashOffset -1 eq {
[] 0 setdash
1 setgray
} {
brushDashArray brushDashOffset setdash
fgred fggreen fgblue setrgbcolor
} ifelse
brushWidth setlinewidth
originalCTM setmatrix
stroke
grestore
} def

/ishow {
0 begin
gsave
fgred fggreen fgblue setrgbcolor
/fontDict printFont printSize scalefont dup setfont def
/descender fontDict begin 0 [FontBBox] 1 get FontMatrix end
transform exch pop def
/vertoffset 1 printSize sub descender sub def {
0 vertoffset moveto show
/vertoffset vertoffset printSize sub def
} forall
grestore
end
} dup 0 3 dict put def
/patternproc {
0 begin
/patternByteLength patternString length def
/patternHeight patternByteLength 8 mul sqrt cvi def
/patternWidth patternHeight def
/patternByteWidth patternWidth 8 idiv def
/imageByteMaxLength imageByteWidth imageHeight mul
stringLimit patternByteWidth sub min def
/imageMaxHeight imageByteMaxLength imageByteWidth idiv patternHeight idiv
patternHeight mul patternHeight max def
/imageHeight imageHeight imageMaxHeight sub store
/imageString imageByteWidth imageMaxHeight mul patternByteWidth add string def
0 1 imageMaxHeight 1 sub {
/y exch def
/patternRow y patternByteWidth mul patternByteLength mod def
/patternRowString patternString patternRow patternByteWidth getinterval def
/imageRow y imageByteWidth mul def
0 patternByteWidth imageByteWidth 1 sub {
/x exch def
imageString imageRow x add patternRowString putinterval
} for
} for
imageString
end
} dup 0 12 dict put def

/min {
dup 3 2 roll dup 4 3 roll lt { exch } if pop
} def

/max {
dup 3 2 roll dup 4 3 roll gt { exch } if pop
} def

/midpoint {
0 begin
/y1 exch def
/x1 exch def
/y0 exch def
/x0 exch def
x0 x1 add 2 div
y0 y1 add 2 div
end
} dup 0 4 dict put def

/thirdpoint {
0 begin
/y1 exch def
/x1 exch def
/y0 exch def
/x0 exch def
x0 2 mul x1 add 3 div
y0 2 mul y1 add 3 div
end
} dup 0 4 dict put def

/subspline {
0 begin
/movetoNeeded exch def
y exch get /y3 exch def
x exch get /x3 exch def
y exch get /y2 exch def
x exch get /x2 exch def
y exch get /y1 exch def
x exch get /x1 exch def
y exch get /y0 exch def
x exch get /x0 exch def
x1 y1 x2 y2 thirdpoint
/p1y exch def
/p1x exch def
x2 y2 x1 y1 thirdpoint
/p2y exch def
/p2x exch def
x1 y1 x0 y0 thirdpoint
p1x p1y midpoint
/p0y exch def
/p0x exch def
x2 y2 x3 y3 thirdpoint
p2x p2y midpoint
/p3y exch def
/p3x exch def
movetoNeeded { p0x p0y moveto } if
p1x p1y p2x p2y p3x p3y curveto
end
} dup 0 17 dict put def

/storexyn {
/n exch def
/y n array def
/x n array def
n 1 sub -1 0 {
/i exch def
y i 3 2 roll put
x i 3 2 roll put
} for
} def

/SSten {
fgred fggreen fgblue setrgbcolor
dup true exch 1 0 0 -1 0 6 -1 roll matrix astore
} def

/FSten {
dup 3 -1 roll dup 4 1 roll exch
newpath
0 0 moveto
dup 0 exch lineto
exch dup 3 1 roll exch lineto
0 lineto
closepath
bgred bggreen bgblue setrgbcolor
eofill
SSten
} def

/Rast {
exch dup 3 1 roll 1 0 0 -1 0 6 -1 roll matrix astore
} def


/arrowhead {
0 begin
transform originalCTM itransform
/taily exch def
/tailx exch def
transform originalCTM itransform
/tipy exch def
/tipx exch def
/dy tipy taily sub def
/dx tipx tailx sub def
/angle dx 0 ne dy 0 ne or { dy dx atan } { 90 } ifelse def
gsave
originalCTM setmatrix
tipx tipy translate
angle rotate
newpath
arrowHeight neg arrowWidth 2 div moveto
0 0 lineto
arrowHeight neg arrowWidth 2 div neg lineto
patternNone not {
originalCTM setmatrix
/padtip arrowHeight 2 exp 0.25 arrowWidth 2 exp mul add sqrt brushWidth mul
arrowWidth div def
/padtail brushWidth 2 div def
tipx tipy translate
angle rotate
padtip 0 translate
arrowHeight padtip add padtail add arrowHeight div dup scale
arrowheadpath
ifill
} if
brushNone not {
originalCTM setmatrix
tipx tipy translate
angle rotate
arrowheadpath
istroke
} if
grestore
end
} dup 0 9 dict put def

/arrowheadpath {
newpath
arrowHeight neg arrowWidth 2 div moveto
0 0 lineto
arrowHeight neg arrowWidth 2 div neg lineto
} def

/leftarrow {
0 begin
y exch get /taily exch def
x exch get /tailx exch def
y exch get /tipy exch def
x exch get /tipx exch def
brushLeftArrow { tipx tipy tailx taily arrowhead } if
end
} dup 0 4 dict put def

/rightarrow {
0 begin
y exch get /tipy exch def
x exch get /tipx exch def
y exch get /taily exch def
x exch get /tailx exch def
brushRightArrow { tipx tipy tailx taily arrowhead } if
end
} dup 0 4 dict put def




Begin
[ 0.799705 0 0 0.799705 0 0 ] concat
/originalCTM matrix currentmatrix def

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 433.125 504.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 433.125 552.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 265.125 504.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 265.125 552.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 137.125 504.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 137.125 552.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 321.125 600.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 489.125 600.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 193.125 600.625 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I Elli
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.5 -0 -0 0.5 144 410 ] concat
453 529 448 32 Elli
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0.75 SetP
[ 0.125 -0 -0 0.125 486.625 598.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
none SetB %I b n
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.084375 -0 -0 0.084375 505.272 606.534 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0.75 SetP
[ 0.125 -0 -0 0.125 318.625 598.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
none SetB %I b n
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.084375 -0 -0 0.084375 337.272 606.534 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0.75 SetP
[ 0.125 -0 -0 0.125 190.625 598.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
none SetB %I b n
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.084375 -0 -0 0.084375 209.272 606.534 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0.75 SetP
[ 0.125 -0 -0 0.125 134.625 502.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
none SetB %I b n
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.084375 -0 -0 0.084375 153.272 510.534 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.125 -0 -0 0.125 262.625 502.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.125 -0 -0 0.125 430.625 502.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I Elli
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 362.875 611.625 ] concat
617 99 16 16 Elli
End

Begin %I Elli
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 378.875 611.625 ] concat
617 99 16 16 Elli
End

Begin %I Line
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.5 -0 -0 0.5 133.5 439.5 ] concat
117 369 181 369 Line
End

Begin %I Line
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.5 -0 -0 0.5 261.5 439.5 ] concat
117 369 181 369 Line
End

Begin %I Line
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.5 -0 -0 0.5 429.5 439.5 ] concat
117 369 181 369 Line
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 179.5 532 ] concat
[
(Procr)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 307.5 532 ] concat
[
(Procr)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 475.5 532 ] concat
[
(Procr)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 235.5 628 ] concat
[
(Mem)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 363.5 628 ] concat
[
(Mem)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 531.5 628 ] concat
[
(Mem)
] Text
End

Begin %I Elli
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.125 -0 -0 0.125 346.875 611.625 ] concat
617 99 16 16 Elli
End

Begin %I BSpl
1 0 1 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.5 -0 -0 0.5 19.5 393.5 ] concat
457 333
473 381
441 365
457 413
4 BSpl
End

Begin %I BSpl
1 0 1 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.5 -0 -0 0.5 147.5 393.5 ] concat
457 333
473 381
441 365
457 413
4 BSpl
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 360 555 ] concat
[
(Remote)
(memory)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 232 555 ] concat
[
(Local)
(memory)
] Text
End

Begin %I BSpl
1 0 1 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 0.5 -0 -0 0.5 315.5 393.5 ] concat
457 333
473 381
441 365
457 413
4 BSpl
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 528 555 ] concat
[
(Remote)
(memory)
] Text
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0.75 SetP
[ 0.125 -0 -0 0.125 134.625 550.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
none SetB %I b n
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.084375 -0 -0 0.084375 153.272 558.534 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.125 -0 -0 0.125 262.625 550.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I CBSpl
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
1 SetP
[ 0.125 -0 -0 0.125 430.625 550.125 ] concat
267 271
267 335
331 335
587 335
651 335
651 271
651 143
651 79
587 79
331 79
267 79
267 143
12 CBSpl
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 177 580 ] concat
[
(Cache)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 305 580 ] concat
[
(Cache)
] Text
End

Begin %I Text
0 0 0 SetCFg
Times-Roman 12 SetF
[ 1 0 0 1 473 580 ] concat
[
(Cache)
] Text
End

Begin %I Line
1 0 0 [] 0 SetB
0 0 0 SetCFg
1 1 1 SetCBg
0 SetP
[ 1 -0 -0 1 60 364 ] concat
132 180 132 196 Line
End

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(from)f(those)i(encountered)4 1173 y(in)e(DMMs.)24 b(The)14
b(high)f(cost)i(of)e(interprocessor)g(communication)g(in)h(distributed)f
(memory)f(multipro-)4 1227 y(cessors)18 b(makes)e(the)h(minimization)e(of)h
(communication)g(the)g(predominant)g(issue)h(in)f(selecting)h(data)4
1282 y(distributions)h(and)i(in)e(partitioning)g(computations.)38
b(On)19 b(SSMMs,)j(a)d(methodology)f(for)h(selecting)4 1336
y(data)14 b(distributions)g(must)g(also)g(consider)g(cache)h(af)o(\256nity)m
(,)f(memory)f(contention)h(and)g(false)g(sharing)g(in)4 1390
y(addition)d(to)g(the)g(cost)h(of)f(interprocessor)g(communication.)17
b(Furthermore,)10 b(the)h(single)h(shared)f(address)4 1444
y(space)j(present)f(in)g(SSMMs)g(provides)g(\257exibility)f(in)h(the)g
(selection)g(of)f(computation)h(partitions.)19 b(This)4 1498
y(should)e(be)f(exploited)g(in)g(applications)h(in)f(which)g(owner)o
(-computes)g(results)g(in)h(poor)f(performance.)4 1552 y(The)f
Fe(Jasmine)g Fo(compiler)f(project)g([2)o(])h(is)g(investigating)f(the)g
(issues)i(discussed)f(in)g(this)f(paper)h(through)4 1607 y(the)d(development)
g(of)g(a)h(framework)e(for)g(automatically)h(deriving)f(data)i(distributions)
e(on)i(SSMMs.)4 1777 y Fn(Refer)o(ences)29 1896 y Fo([1])24
b(T)l(.S.)17 b(Abdelrahman)f(et)g(al.)29 b(An)16 b(overview)f(of)h(the)g
(NUMAchine)h(multiprocessor)e(project.)28 b(In)112 1943 y Fe(Pr)n(oc.)13
b(of)g(the)f(Canadian)g(Super)n(computing)g(Conf.)p Fo(,)h(pages)g
(283\261295,)f(1994.)29 2032 y([2])24 b(T)l(.S.)12 b(Abdelrahman,)f(N.)h
(Manjikian,)g(and)f(S.)g(T)m(andri.)16 b(The)11 b(Jasmine)h(Compiler.)k(In)10
b(preparation.)29 2120 y([3])24 b(T)l(.S.)e(Abdelrahman)e(and)h(T)l(.N.)h(W)l
(ong.)41 b(Distributed)20 b(array)g(data)h(management)g(on)f(NUMA)112
2167 y(multiprocessors.)d(In)12 b Fe(Pr)n(oc.)i(of)e(SHPCC)p
Fo(,)i(pages)f(551\261559,)f(1994.)29 2256 y([4])24 b(S.P)-6
b(.)10 b(Amarasinghe,)g(J.M.)h(Anderson,)f(M.S.)h(Lam,)g(and)e(A.W)-5
b(.)11 b(Lim.)j(An)9 b(overview)g(of)g(a)h(compiler)112 2303
y(for)k(scalable)j(parallel)e(machines.)27 b(In)15 b Fe(Languages)h(and)f
(Compilers)i(for)f(Parallel)g(Computing)p Fo(,)112 2350 y(pages)c
(253\261272.)h(Springer)o(-V)-6 b(erlag)10 b(LNCS-768,)j(1993.)29
2438 y([5])24 b(J.M.)13 b(Anderson.)j(Demonstration)11 b(of)g(automatic)g
(data)h(and)f(computation)g(decomposition)g(tech-)112 2485
y(niques.)f(In)e Fe(Pr)n(oc.)g(of)g(the)g(W)-5 b(orkshop)8
b(on)g(Automatic)g(Data)g(Layout)g(and)g(Performance)g(Pr)n(ediction)p
Fo(,)112 2532 y(1995.)29 2620 y([6])24 b(V)-6 b(.)12 b(Balasundaram,)i(G.)f
(Fox,)g(K.)g(Kennedy)m(,)g(and)f(U.)i(Kremer)m(.)k(A)13 b(static)g
(performance)e(estimator)112 2667 y(to)h(guide)g(data)g(partitioning)f
(decisions.)19 b(In)12 b Fe(Pr)n(oc.)i(of)e(PPOPP)p Fo(,)j(pages)e
(213\261223,)f(1991.)29 2756 y([7])24 b(R.)9 b(Bixby)m(,)h(K.)g(Kennedy)m(,)f
(and)h(U.)f(Kremer)m(.)j(Automatic)d(data)g(layout)f(using)h(0-1)g(integer)f
(program-)112 2803 y(ming.)15 b(In)c Fe(Pr)n(oc.)i(of)e(the)g(Int'l)f(Conf.)i
(on)f(Parallel)g(Ar)n(chitectur)n(es)i(and)e(Compilation)g(T)-5
b(echniques)p Fo(,)112 2850 y(pages)12 b(111\261122,)h(1994.)p
eop
%%Page: 10 10
10 9 bop 29 -27 a Fo([8])24 b(W)-5 b(.J.)19 b(Bolosky)f(and)g(M.L.)h(Scott.)
32 b(False)18 b(sharing)f(and)h(its)g(ef)o(fect)f(on)g(shared)h(memory)f
(multi-)112 20 y(processors.)k(In)13 b Fe(Pr)n(oc.)j(of)d(4th)g(Symp.)h(on)g
(Experiences)h(with)e(Distributed)h(and)f(Multipr)n(ocessor)112
67 y(Systems)p Fo(,)g(pages)g(57\26171,)f(1993.)29 155 y([9])24
b(B.M.)14 b(Chapman,)g(T)l(.)h(Fahringer)n(,)e(and)g(H.)h(Zima.)21
b(Automatic)12 b(support)h(for)f(data)i(distribution)e(on)112
202 y(distributed)g(memory)g(multiprocessor)g(systems.)22 b(In)12
b Fe(Languages)h(and)g(Compilers)h(for)f(Parallel)112 249 y(Computing)p
Fo(,)f(pages)h(184\261199.)f(Springer)o(-V)-6 b(erlag)11 b(LNCS-768,)h(1993.)
4 337 y([10])24 b(B.)11 b(Gamsa.)k(Region-oriented)9 b(main)h(memory)f
(management)h(in)g(shared-memory)f(NUMA)i(mul-)112 384 y(tiprocessors.)19
b(Master)r(')m(s)13 b(thesis,)h(Department)d(of)i(Computer)f(Science,)h
(University)f(of)g(T)m(oronto,)112 431 y(T)m(oronto,)f(CANADA,)i(1992.)4
519 y([11])24 b(J.)f(Garcia,)h(E.)f(A)-5 b(yguade,)26 b(and)c(J.)h(Labarta.)
44 b(A)22 b(novel)g(approach)g(towards)g(automatic)g(data)112
566 y(distribution.)33 b(In)18 b Fe(Pr)n(oc.)i(of)e(the)h(W)-5
b(orkshop)20 b(on)e(Automatic)g(Data)g(Layout)g(and)h(Performance)112
613 y(Pr)n(ediction)p Fo(,)13 b(1995.)4 701 y([12])24 b(M.)16
b(Gupta)f(and)h(P)-6 b(.)17 b(Banerjee.)27 b(Automatic)15 b(data)g
(partitioning)g(on)g(distributed)g(memory)g(multi-)112 748
y(processors.)j Fe(IEEE)c(T)m(rans.)f(on)f(Parallel)h(and)f(Distributed)h
(Systems)p Fo(,)g(3\(2\):179\261193,)e(1992.)4 836 y([13])24
b(K.)15 b(Harzallah)g(and)g(K.C.)h(Sevcik.)25 b(Hot)15 b(spot)g(analysis)g
(in)g(lar)o(ge)g(scale)h(shared)f(memory)f(multi-)112 883 y(processors.)k(In)
12 b Fe(Pr)n(oc.)i(of)e(Super)n(computing'93)p Fo(,)g(pages)h(895\261905.)f
(ACM,)i(1993.)4 971 y([14])24 b(M.)11 b(Heinrich)f(et)h(al.)16
b(The)11 b(Stanford)f(FLASH)g(Multiprocessor.)16 b(In)10 b
Fe(Pr)n(oc.)i(of)f(the)g(21st)g(Int'l)e(Symp.)112 1018 y(on)j(Computer)g(Ar)n
(chitectur)n(e)p Fo(,)j(pages)e(302\261313,)f(1994.)4 1106
y([15])24 b(S.)15 b(Hiranandani,)i(K.)f(Kennedy)m(,)g(and)g(C.)g(T)m(seng.)27
b(Compiler)15 b(optimizations)g(for)g(Fortran)f(D)i(on)112
1153 y(MIMD)f(distributed-memory)e(machines.)25 b(In)15 b Fe(Pr)n(oc.)h(of)f
(Super)n(computing'91)p Fo(,)g(pages)h(86\261100,)112 1200
y(Albuquerque,)c(NM,)h(1991.)4 1288 y([16])24 b(HPF)l(.)33
b(High)17 b(Performance)g(Fortran)g(Language)i(Speci\256cation)e(\(High)g
(Performance)g(Fortran)112 1335 y(Forum\).)f(T)m(echnical)d(report)e
(CRPC-TR92225,)i(Rice)g(University)m(,)f(1994.)4 1424 y([17])24
b(C.)13 b(Koelbel.)18 b(HPF)12 b(constraints.)18 b(Personal)12
b(Communications,)g(1995.)4 1512 y([18])24 b(U.)14 b(Kremer)m(.)23
b(Automatic)14 b(data)g(layout)g(for)g(distributed-memory)e(multiprocessors.)
23 b(T)m(echnical)112 1559 y(report)11 b(CRPC-TR93229-S,)h(Center)h(for)e
(Research)i(on)f(Parallel)g(Computation,)g(1993.)4 1647 y([19])24
b(T)l(.T)l(.)15 b(Kwan,)f(B.K.)h(T)m(otty)m(,)e(and)g(D.A.)h(Reed.)21
b(Communication)12 b(and)i(computation)e(performance)112 1694
y(of)f(the)i(CM5.)19 b(In)12 b Fe(Pr)n(oc.)h(of)g(Super)n(computing'93)p
Fo(,)f(pages)h(192\261201.)f(ACM,)h(1993.)4 1782 y([20])24
b(D.)15 b(Lenoski)h(et)f(al.)26 b(The)15 b(Stanford)f(DASH)h(multiprocessor)m
(.)25 b Fe(IEEE)16 b(Computer)p Fo(,)h(25\(3\):63\26179,)112
1829 y(1992.)4 1917 y([21])24 b(H.)12 b(Li)g(and)g(K.C.)h(Sevcik.)k
(Numacros:)g(Data)12 b(parallel)f(programming)f(on)i(NUMA)g(multiproces-)112
1964 y(sors.)h(In)c Fe(Pr)n(oc.)i(of)e(4th)g(Symp.)h(on)g(Experiences)g(with)
g(Distributed)f(and)g(Multipr)n(ocessor)j(Systems)p Fo(,)112
2011 y(pages)g(247\261263,)h(1993.)4 2099 y([22])24 b(J.)11
b(Li)h(and)f(M.)h(Chen.)k(Compiling)10 b(communication-ef)o(\256cient)f
(programs)i(for)f(massively)h(parallel)112 2146 y(machines.)18
b Fe(Journal)12 b(of)h(Parallel)f(and)h(Distributed)f(Computing)p
Fo(,)g(2\(3\):361\261376,)f(1991.)4 2234 y([23])24 b(Cray)14
b(Research.)25 b(The)16 b(Cray)e(Research)h(Massively)h(Parallel)e(Processor)
g(System)h(-)f(Cray)h(T3D.)112 2281 y(T)m(echnical)d(report)f(80922,)i
(Munchen,)g(Germany)m(,)f(1993.)4 2369 y([24])24 b(Kendall)12
b(Square)f(Research.)19 b Fe(KSR1)13 b(Principles)h(of)e(Operation)p
Fo(.)18 b(W)l(altham,)13 b(MA,)g(1991.)4 2457 y([25])24 b(J.)12
b(T)m(orres,)g(E.)h(A)-5 b(yguade,)13 b(J.)g(Labarta,)f(and)g(M.)h(V)-6
b(alero.)17 b(Align)12 b(and)g(distribute-based)f(linear)g(loop)112
2504 y(transformations.)16 b(In)11 b Fe(Languages)g(and)h(Compilers)h(for)f
(Parallel)g(Computing)p Fo(,)g(pages)g(321\261339.)112 2551
y(Springer)o(-V)-6 b(erlag)10 b(LNCS-768,)j(1993.)4 2639 y([26])24
b(Z.)17 b(V)m(ranesic,)h(M.)f(Stumm,)f(R.)i(White,)f(and)f(D.)h(Lewis.)30
b(The)16 b(Hector)g(Multiprocessor.)29 b Fe(IEEE)112 2686 y(Computer)p
Fo(,)13 b(24\(1\):72\26180,)e(1991.)4 2774 y([27])24 b(R.W)-5
b(.)12 b(W)n(isniewski,)g(L.I.)g(Kontothanassis,)h(and)e(M.L.)h(Scott.)k
(High)11 b(performance)e(synchroniza-)112 2821 y(tion)i(algorithms)h(for)g
(multiprogrammed)e(multiprocessors.)18 b(In)12 b Fe(Pr)n(oc.)h(of)g(PPOPP)p
Fo(,)h(1995.)p eop
%%Trailer
end
userdict /end-hook known{end-hook}if
%%EOF

Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Tandri_Abdel_PDPTA95.ps version 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%!PS-Adobe-2.0
%%Creator: dvips 5.512 Copyright 1986, 1993 Radical Eye Software
%%Title: pdpta.dvi
%%CreationDate: Thu Nov 23 17:27:55 1995
%%Pages: 10
%%PageOrder: Ascend
%%BoundingBox: 0 0 612 792
%%DocumentFonts: Times-Bold Times-Roman Times-Italic Courier
%%EndComments
%DVIPSCommandLine: dvips -o pdpta.ps pdpta.dvi
%DVIPSSource:  TeX output 1995.08.11:1234
%%BeginProcSet: tex.pro
/TeXDict 250 dict def TeXDict begin /N{def}def /B{bind def}N /S{exch}N /X{S N}
B /TR{translate}N /isls false N /vsize 11 72 mul N /@rigin{isls{[0 -1 1 0 0 0]
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%%Page: 9 9
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702 y(data)g(regions)f(to)h(reduce)g(false)g(sharing.)31 b(This)17
b(technique)g(is)g(oblivious)f(to)h(SSMM)g(speci\256c)g(issues)4
756 y(such)c(as)g(contention)f(and)g(cache)h(af)o(\256nity)m(.)4
938 y Fn(7)71 b(Concluding)19 b(Remarks)4 1065 y Fo(Although)9
b(lar)o(ge)g(SSMMs)i(are)e(built)g(based)h(on)g(an)g(architecture)e(with)i
(distributed)f(memory)m(,)g(the)h(shared)4 1119 y(memory)15
b(paradigm)g(introduces)g(performance)g(issues)i(that)e(are)h(dif)o(ferent)f
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1282 y(distributions)h(and)i(in)e(partitioning)g(computations.)38
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y(addition)d(to)g(the)g(cost)h(of)f(interprocessor)g(communication.)17
b(Furthermore,)10 b(the)h(single)h(shared)f(address)4 1444
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(issues)i(discussed)f(in)g(this)f(paper)h(through)4 1607 y(the)d(development)
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e(on)i(SSMMs.)4 1777 y Fn(Refer)o(ences)29 1896 y Fo([1])24
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2167 y(multiprocessors.)d(In)12 b Fe(Pr)n(oc.)i(of)e(SHPCC)p
Fo(,)i(pages)f(551\261559,)f(1994.)29 2256 y([4])24 b(S.P)-6
b(.)10 b(Amarasinghe,)g(J.M.)h(Anderson,)f(M.S.)h(Lam,)g(and)e(A.W)-5
b(.)11 b(Lim.)j(An)9 b(overview)g(of)g(a)h(compiler)112 2303
y(for)k(scalable)j(parallel)e(machines.)27 b(In)15 b Fe(Languages)h(and)f
(Compilers)i(for)f(Parallel)g(Computing)p Fo(,)112 2350 y(pages)c
(253\261272.)h(Springer)o(-V)-6 b(erlag)10 b(LNCS-768,)j(1993.)29
2438 y([5])24 b(J.M.)13 b(Anderson.)j(Demonstration)11 b(of)g(automatic)g
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y(niques.)f(In)e Fe(Pr)n(oc.)g(of)g(the)g(W)-5 b(orkshop)8
b(on)g(Automatic)g(Data)g(Layout)g(and)g(Performance)g(Pr)n(ediction)p
Fo(,)112 2532 y(1995.)29 2620 y([6])24 b(V)-6 b(.)12 b(Balasundaram,)i(G.)f
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(performance)e(estimator)112 2667 y(to)h(guide)g(data)g(partitioning)f
(decisions.)19 b(In)12 b Fe(Pr)n(oc.)i(of)e(PPOPP)p Fo(,)j(pages)e
(213\261223,)f(1991.)29 2756 y([7])24 b(R.)9 b(Bixby)m(,)h(K.)g(Kennedy)m(,)f
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(program-)112 2803 y(ming.)15 b(In)c Fe(Pr)n(oc.)i(of)e(the)g(Int'l)f(Conf.)i
(on)f(Parallel)g(Ar)n(chitectur)n(es)i(and)e(Compilation)g(T)-5
b(echniques)p Fo(,)112 2850 y(pages)12 b(111\261122,)h(1994.)p
eop
%%Page: 10 10
10 9 bop 29 -27 a Fo([8])24 b(W)-5 b(.J.)19 b(Bolosky)f(and)g(M.L.)h(Scott.)
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(Experiences)h(with)e(Distributed)h(and)f(Multipr)n(ocessor)112
67 y(Systems)p Fo(,)g(pages)g(57\26171,)f(1993.)29 155 y([9])24
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(University)f(of)g(T)m(oronto,)112 431 y(T)m(oronto,)f(CANADA,)i(1992.)4
519 y([11])24 b(J.)f(Garcia,)h(E.)f(A)-5 b(yguade,)26 b(and)c(J.)h(Labarta.)
44 b(A)22 b(novel)g(approach)g(towards)g(automatic)g(data)112
566 y(distribution.)33 b(In)18 b Fe(Pr)n(oc.)i(of)e(the)h(W)-5
b(orkshop)20 b(on)e(Automatic)g(Data)g(Layout)g(and)h(Performance)112
613 y(Pr)n(ediction)p Fo(,)13 b(1995.)4 701 y([12])24 b(M.)16
b(Gupta)f(and)h(P)-6 b(.)17 b(Banerjee.)27 b(Automatic)15 b(data)g
(partitioning)g(on)g(distributed)g(memory)g(multi-)112 748
y(processors.)j Fe(IEEE)c(T)m(rans.)f(on)f(Parallel)h(and)f(Distributed)h
(Systems)p Fo(,)g(3\(2\):179\261193,)e(1992.)4 836 y([13])24
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(in)g(lar)o(ge)g(scale)h(shared)f(memory)f(multi-)112 883 y(processors.)k(In)
12 b Fe(Pr)n(oc.)i(of)e(Super)n(computing'93)p Fo(,)g(pages)h(895\261905.)f
(ACM,)i(1993.)4 971 y([14])24 b(M.)11 b(Heinrich)f(et)h(al.)16
b(The)11 b(Stanford)f(FLASH)g(Multiprocessor.)16 b(In)10 b
Fe(Pr)n(oc.)i(of)f(the)g(21st)g(Int'l)e(Symp.)112 1018 y(on)j(Computer)g(Ar)n
(chitectur)n(e)p Fo(,)j(pages)e(302\261313,)f(1994.)4 1106
y([15])24 b(S.)15 b(Hiranandani,)i(K.)f(Kennedy)m(,)g(and)g(C.)g(T)m(seng.)27
b(Compiler)15 b(optimizations)g(for)g(Fortran)f(D)i(on)112
1153 y(MIMD)f(distributed-memory)e(machines.)25 b(In)15 b Fe(Pr)n(oc.)h(of)f
(Super)n(computing'91)p Fo(,)g(pages)h(86\261100,)112 1200
y(Albuquerque,)c(NM,)h(1991.)4 1288 y([16])24 b(HPF)l(.)33
b(High)17 b(Performance)g(Fortran)g(Language)i(Speci\256cation)e(\(High)g
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b(C.)13 b(Koelbel.)18 b(HPF)12 b(constraints.)18 b(Personal)12
b(Communications,)g(1995.)4 1512 y([18])24 b(U.)14 b(Kremer)m(.)23
b(Automatic)14 b(data)g(layout)g(for)g(distributed-memory)e(multiprocessors.)
23 b(T)m(echnical)112 1559 y(report)11 b(CRPC-TR93229-S,)h(Center)h(for)e
(Research)i(on)f(Parallel)g(Computation,)g(1993.)4 1647 y([19])24
b(T)l(.T)l(.)15 b(Kwan,)f(B.K.)h(T)m(otty)m(,)e(and)g(D.A.)h(Reed.)21
b(Communication)12 b(and)i(computation)e(performance)112 1694
y(of)f(the)i(CM5.)19 b(In)12 b Fe(Pr)n(oc.)h(of)g(Super)n(computing'93)p
Fo(,)f(pages)h(192\261201.)f(ACM,)h(1993.)4 1782 y([20])24
b(D.)15 b(Lenoski)h(et)f(al.)26 b(The)15 b(Stanford)f(DASH)h(multiprocessor)m
(.)25 b Fe(IEEE)16 b(Computer)p Fo(,)h(25\(3\):63\26179,)112
1829 y(1992.)4 1917 y([21])24 b(H.)12 b(Li)g(and)g(K.C.)h(Sevcik.)k
(Numacros:)g(Data)12 b(parallel)f(programming)f(on)i(NUMA)g(multiproces-)112
1964 y(sors.)h(In)c Fe(Pr)n(oc.)i(of)e(4th)g(Symp.)h(on)g(Experiences)g(with)
g(Distributed)f(and)g(Multipr)n(ocessor)j(Systems)p Fo(,)112
2011 y(pages)g(247\261263,)h(1993.)4 2099 y([22])24 b(J.)11
b(Li)h(and)f(M.)h(Chen.)k(Compiling)10 b(communication-ef)o(\256cient)f
(programs)i(for)f(massively)h(parallel)112 2146 y(machines.)18
b Fe(Journal)12 b(of)h(Parallel)f(and)h(Distributed)f(Computing)p
Fo(,)g(2\(3\):361\261376,)f(1991.)4 2234 y([23])24 b(Cray)14
b(Research.)25 b(The)16 b(Cray)e(Research)h(Massively)h(Parallel)e(Processor)
g(System)h(-)f(Cray)h(T3D.)112 2281 y(T)m(echnical)d(report)f(80922,)i
(Munchen,)g(Germany)m(,)f(1993.)4 2369 y([24])24 b(Kendall)12
b(Square)f(Research.)19 b Fe(KSR1)13 b(Principles)h(of)e(Operation)p
Fo(.)18 b(W)l(altham,)13 b(MA,)g(1991.)4 2457 y([25])24 b(J.)12
b(T)m(orres,)g(E.)h(A)-5 b(yguade,)13 b(J.)g(Labarta,)f(and)g(M.)h(V)-6
b(alero.)17 b(Align)12 b(and)g(distribute-based)f(linear)g(loop)112
2504 y(transformations.)16 b(In)11 b Fe(Languages)g(and)h(Compilers)h(for)f
(Parallel)g(Computing)p Fo(,)g(pages)g(321\261339.)112 2551
y(Springer)o(-V)-6 b(erlag)10 b(LNCS-768,)j(1993.)4 2639 y([26])24
b(Z.)17 b(V)m(ranesic,)h(M.)f(Stumm,)f(R.)i(White,)f(and)f(D.)h(Lewis.)30
b(The)16 b(Hector)g(Multiprocessor.)29 b Fe(IEEE)112 2686 y(Computer)p
Fo(,)13 b(24\(1\):72\26180,)e(1991.)4 2774 y([27])24 b(R.W)-5
b(.)12 b(W)n(isniewski,)g(L.I.)g(Kontothanassis,)h(and)e(M.L.)h(Scott.)k
(High)11 b(performance)e(synchroniza-)112 2821 y(tion)i(algorithms)h(for)g
(multiprogrammed)e(multiprocessors.)18 b(In)12 b Fe(Pr)n(oc.)h(of)g(PPOPP)p
Fo(,)h(1995.)p eop
%%Trailer
end
userdict /end-hook known{end-hook}if
%%EOF

Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/Unrau_PhD.ps.Z version [32bddefae3].

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#!/bin/sh
#
# to run (if called headerize): headerize <text> < in_file > out_file
# e.g.: if heading is: "a heading", source file is sfile.ps, destination
#       file is dfile.ps, then use:
#
#       headerize a heading < sfile.ps > dfile.ps
# or
#       headerize "a heading" < sfile.ps > dfile.ps
#
gawk -v MYHEADING="$*" '
    BEGIN{
        begin=1
    }
    begin==1 && $1 !~ /^%.*/ {
        begin=0
        printf "save\n"
        printf "gsave\n"
        printf "/Times-Italic findfont 9 scalefont setfont\n"
        printf "72 750 moveto (%s) show\n", MYHEADING
        printf "grestore\n"
        printf "restore\n"
    }
    {
        print
    }
    '

Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/OLD/ldreport.ps.Z version [a667289c44].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Parsons_Sevcik_IPPS95.ps.Z version [10a026c65e].

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/README.Z version [2cf48fe915].

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#!/bin/sh
#
# to run (if called headerize): headerize <text> < in_file > out_file
# e.g.: if heading is: "a heading", source file is sfile.ps, destination
#       file is dfile.ps, then use:
#
#       headerize a heading < sfile.ps > dfile.ps
# or
#       headerize "a heading" < sfile.ps > dfile.ps
#
gawk -v MYHEADING="$*" '
    BEGIN{
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    begin==1 && $1 !~ /^%.*/ {
        begin=0
        printf "save\n"
        printf "gsave\n"
        printf "/Times-Italic findfont 9 scalefont setfont\n"
        printf "72 750 moveto (%s) show\n", MYHEADING
        printf "grestore\n"
        printf "restore\n"
    }
    {
        print
    }
    '

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<!-- RCS $Id: Welcome.html,v 1.2 1994/11/02 16:13:18 caranci Exp caranci -->
<HTML>
<body bgcolor="#ffffff" text="#000000"  link="#0000ff" vlink="#aaaaff" alink="#0077FF"> </body>
<FONT SIZE=4>

<HEAD>
<TITLE>Parallel Systems Group: Home page</TITLE>
</HEAD>

<BODY>
<H1><img align="center" src="../EECG/RESEARCH/ParallelSys/images/newban_t.gif"></A>
Parallel Systems Group</H1>

<HR>

The Parallel Systems Group comprises of researchers from the
<A HREF="http://www.utoronto.ca/uoft.html">University of Toronto</A> 
working in all aspects of parallel systems,
including computer architecture, operating systems, compilers, performance 
evaluation and applications.
<P>

Previous projects include the <A HREF="hector.html">Hector</A> shared 
memory multiprocessor, and the 
<A HREF="hurricane.html">Hurricane</A> multiprocessor operating system.
<P>

The group is currently building the 
<A HREF="parallel/NUMA.Welcome.html">NUMAchine</A> multiprocessor, the
<A HREF="tornado.html">Tornado</A> operating system, and the
<A HREF="../~tsa/jasmine.html">Jasmine</A> compiler.
<P>

<BR>
<BR>
<BR>
<center>
<A HREF="publications.html">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/publ_button.gif"></A>
<P>
<A HREF="people.html">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/people_button.gif"></A>
<P>
<A HREF="parallel/projects.html">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/proj_button.gif"></A>
<P>
<BR>
<BR>
<BR>

<H2>Other Resources</H2>

<H3>University of Toronto Resources</H3>
<UL>
<LI><A HREF="http://www.hprc.utoronto.ca">
University of Toronto High Performance Computing Research Center </A>
<LI><A HREF="http://www.eecg.toronto.edu/EECG/EECGhome.html">
University of Toronto Electrical Engineering Computer Group</A>
<LI><A HREF="http://www.cdf.toronto.edu"> 
University of Toronto Department of Computer Science</A>
</UL>


<H3>Computing Resources</H3>
<UL>
<LI><A HREF="http://www.ccsf.caltech.edu/other_sites.html">
Supercomputing Web pages</A>
<LI><A HREF="http://www.cs.cmu.edu/afs/cs.cmu.edu/project/scandal/public/www/research-groups.html">
Supercomputing & Parallel Computing Research Groups</A>
<LI><A HREF="http://www.cs.dartmouth.edu/pario.html">
Parallel I/O archive at Dartmouth</A>
</UL>

<EM>
<!-- <HR> These pages will look best if displayed with the <A HREF="http://home.mcom.com/home/faq_docs/faq_client.html"> Mosaic Netscape</A> web browser.  Check it out!<BR> <HR> -->
This is still a work in progress... Mail suggestions to:<BR>
<A HREF="mailto:kulki@cs.toronto.edu"> kulki </A> or
<A HREF="mailto:okrieg@eecg.toronto.edu"> Orran </A> 

</EM>

</BODY>
</HTML>

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<TITLE>Hector</TITLE>
<H1>Hector</H1>
<P>
Under Construction.
<P>

<A HREF="pubs_abs.html#Stumm_Vranesic_White_IPPS93"> Hector</A>
is a shared memory multiprocessor based on a hierarchy of unidirectional
slotted rings. The main objective was a simple architecture that is 
size and generation scalable. The machine was built from scratch 
with off-the-shelf processors. Please see 
<a href="publications.html">publications</a>
for details such as performance.
 
<HR>

<h3> Hector Processor Board </h3>

<IMG ALIGN=LEFT HSPACE=15 SRC="hectorboard.gif">

<BR>
Each board contains:
<ul>
<li> MC88100 cpu
<li> 4 MB of memory
<li> 16 KB of data cache
<li> 16 KB of instruction cache
</ul>
<BR CLEAR=ALL>

<HR>

<h3> Hector System </h3>
<IMG ALIGN=RIGHT SRC="hector-sys-raw.gif">

<BR>
This system contains:
<ul>
<li> 16 MC88100 cpus
<li> 16 x 4 MB memory
<li> ring interconnect
</ul>
<BR CLEAR=ALL>

<HR>

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<TITLE>Hurricane</TITLE>
<!-- Changed by: Orran Y. Krieger,  2-Oct-1995 -->
<H1>Hurricane</H1>
<P>
Under Construction
<P>

The <A HREF="pubs_abs.html#Unrau_etal_JSC94">Hurricane</A>
operating system is a hierarchically clustered operating system
implemented on the Hector multiprocessor.
 <P>
Hierarchical clustering manages the system resources in clusters, using
tight coupling within a cluster, and loose coupling across clusters.
Distributed systems principles are applied by distributing and
replicating system services and data objects to increase locality,
increase concurrency, and to avoid centralized bottlenecks, thus making
the system scalable.  However, tight coupling is used within a cluster,
so the system performs well for local interactions.  Hierarchical
clustering maximizes locality which is key to good performance in large
systems, and systems based on hierarchical clustering can easily be
adapted to different hardware configurations and architectures by
changing the size of the clusters.  Finally, hierarchical clustering
leads to a modular system composed from easy-to-design and hence
efficient building blocks.
 <P>
All the papers are available from  <A HREF="publications.html#os"> here.</A> 
</UL>


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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
   <TITLE> NUMAchine Home Page </TITLE>
   <META NAME="GENERATOR" CONTENT="Mozilla/3.0Gold (X11; I; SunOS 5.5 sun4m) [Netscape]">
</HEAD>
<BODY BACKGROUND="images/maple_back.gif">

<CENTER><P><IMG SRC="numahw/NUMAchine-med.gif" > <clear=left><BR>
<BR>
</P></CENTER>

<H2 ALIGN=CENTER>The NUMAchine Multiprocessor Project</H2>

<P>The <I>NUMAchine</I> project at the <A HREF="http://www.utoronto.ca/uoft.html">University
of Toronto</A> is a major research project aimed at developing a shared-memory
multiprocessor architecture and software support for easy and efficient
use of this architecture. Members of both the <A HREF="http://www.ece.toronto.edu/">Department
of Electrical and Computer Engineering</A> and the <A HREF="http://www.cs.toronto.edu">Department
of Computer Science</A> are collaborating on this project.</P>

<P>A key objective is to develop a high-performance architecture that is
modular, cost-effective and scalable. At the present time, a prototype
machine is being designed and built, and the system software is being developed.
Follow the links below for more information.
</P>

<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=0 WIDTH="100%">
<TR ALIGN=LEFT VALIGN=CENTER>
<TD WIDTH="65%">


<P>
<IMG SRC="images/computer.gif" ALIGN=CENTER HSPACE=5>
<A HREF="numahw/numahw.html">Hardware description with photographs</A>
</P>

<P>
<IMG SRC="images/archiv.gif" ALIGN=CENTER HSPACE=5>
<A HREF="numadocs.html">Papers and technical documentation</A>
</P>


<P>
<IMG SRC="images/disk.gif" HSPACE=5 ALIGN=CENTER>
System software:
</P>


<UL>
<P>
<IMG SRC="images/wh_ball.gif" HSPACE=5 HEIGHT=16 WIDTH=17 ALIGN=BOTTOM>
<A HREF="tornado.html">The Tornado Operating System</A><BR>
<BR>
</P>

<P>
<IMG SRC="images/wh_ball.gif" HSPACE=5 HEIGHT=16 WIDTH=17 ALIGN=BOTTOM>
<A HREF="../../~tsa/jasmine.html">The Jasmine Compiler</A>
</P>
</UL>

<TD>
<P ALIGN=CENTER>Click on the figures below for the<BR>
                NUMAchine architecture and a hardware photo.<BR>
<A HREF="images/NUMAfig.gif">
<IMG ALIGN=LEFT WIDTH=80 HEIGHT=80 SRC="images/NUMAfig.gif"> 
</A>
<A HREF="numahw/pictures/dbgstn.jpg">
<IMG ALIGN=RIGHT WIDTH=80 HEIGHT=80 SRC="numahw/numa2.gif"> 
</A>
</P>
</TD>
</TABLE>

<P>
<HR WIDTH="100%"></P>

<P>Major funding from:<BR>
<IMG HSPACE=5 VSPACE=5 SRC="images/NSERC.gif" ALIGN=CENTER>
<A HREF="http://www.nserc.ca">Natural Sciences and Engineering Research Council of Canada (NSERC)</A>
</P>

</BODY>
</HTML>

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<TITLE>Hector</TITLE>
<H1>Hector</H1>
<P>
Under Construction.
<P>

<A HREF="http://www.eecg.toronto.edu/parallel/parallel/pubs_abs.html#Stumm_Vranesic_White_IPPS93"> Hector</A>
is a shared memory multiprocessor based on a hierarchy of unidirectional
slotted rings. The main objective was a simple architecture that is 
size and generation scalable. The machine was built from scratch 
with off-the-shelf processors. Please see 
<a href="http://www.eecg.toronto.edu/parallel/parallel/publications.html">publications</a>
for details such as performance.
 
<HR>

<h3> Hector Processor Board </h3>

<IMG ALIGN=LEFT HSPACE=15 SRC="hectorboard.gif">

<BR>
Each board contains:
<ul>
<li> MC88100 cpu
<li> 4 MB of memory
<li> 16 KB of data cache
<li> 16 KB of instruction cache
</ul>
<BR CLEAR=ALL>

<HR>

<h3> Hector System </h3>
<IMG ALIGN=RIGHT SRC="hector-sys-raw.gif">

<BR>
This system contains:
<ul>
<li> 16 MC88100 cpus
<li> 16 x 4 MB memory
<li> ring interconnect
</ul>
<BR CLEAR=ALL>

<HR>

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<TITLE>Hurricane</TITLE>
<!-- Changed by: Orran Y. Krieger,  2-Oct-1995 -->
<H1>Hurricane</H1>
<P>
Under Construction
<P>

The <A HREF="http://www.eecg.toronto.edu/parallel/parallel/pubs_abs.html#Unrau_etal_JSC94">Hurricane</A>
operating system is a hierarchically clustered operating system
implemented on the Hector multiprocessor.
 <P>
Hierarchical clustering manages the system resources in clusters, using
tight coupling within a cluster, and loose coupling across clusters.
Distributed systems principles are applied by distributing and
replicating system services and data objects to increase locality,
increase concurrency, and to avoid centralized bottlenecks, thus making
the system scalable.  However, tight coupling is used within a cluster,
so the system performs well for local interactions.  Hierarchical
clustering maximizes locality which is key to good performance in large
systems, and systems based on hierarchical clustering can easily be
adapted to different hardware configurations and architectures by
changing the size of the clusters.  Finally, hierarchical clustering
leads to a modular system composed from easy-to-design and hence
efficient building blocks.
 <P>
All the papers are available from  <A HREF="http://www.eecg.toronto.edu/parallel/parallel/publications.html#os"> here.</A> 
</UL>


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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
   <TITLE> NUMAchine Home Page </TITLE>
   <META NAME="GENERATOR" CONTENT="Mozilla/3.0Gold (X11; I; SunOS 5.5 sun4m) [Netscape]">
</HEAD>
<BODY BACKGROUND="images/maple_back.gif">

<CENTER><P><IMG SRC="numahw/NUMAchine-med.gif" > <clear=left><BR>
<BR>
</P></CENTER>

<H2 ALIGN=CENTER>The NUMAchine Multiprocessor Project</H2>

<P>The <I>NUMAchine</I> project at the <A HREF="http://www.utoronto.ca/uoft.html">University
of Toronto</A> is a major research project aimed at developing a shared-memory
multiprocessor architecture and software support for easy and efficient
use of this architecture. Members of both the <A HREF="http://www.ece.toronto.edu/">Department
of Electrical and Computer Engineering</A> and the <A HREF="http://www.cs.toronto.edu">Department
of Computer Science</A> are collaborating on this project.</P>

<P>A key objective is to develop a high-performance architecture that is
modular, cost-effective and scalable. At the present time, a prototype
machine is being designed and built, and the system software is being developed.
Follow the links below for more information.
</P>

<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=0 WIDTH="100%">
<TR ALIGN=LEFT VALIGN=CENTER>
<TD WIDTH="65%">


<P>
<IMG SRC="images/computer.gif" ALIGN=CENTER HSPACE=5>
<A HREF="numahw/numahw.html">Hardware description with photographs</A>
</P>

<P>
<IMG SRC="images/archiv.gif" ALIGN=CENTER HSPACE=5>
<A HREF="numadocs.html">Papers and technical documentation</A>
</P>


<P>
<IMG SRC="images/disk.gif" HSPACE=5 ALIGN=CENTER>
System software:
</P>


<UL>
<P>
<IMG SRC="images/wh_ball.gif" HSPACE=5 HEIGHT=16 WIDTH=17 ALIGN=BOTTOM>
<A HREF="tornado.html">The Tornado Operating System</A><BR>
<BR>
</P>

<P>
<IMG SRC="images/wh_ball.gif" HSPACE=5 HEIGHT=16 WIDTH=17 ALIGN=BOTTOM>
<A HREF="../../~tsa/jasmine.html">The Jasmine Compiler</A>
</P>
</UL>

<TD>
<P ALIGN=CENTER>Click on the figures below for the<BR>
                NUMAchine architecture and a hardware photo.<BR>
<A HREF="images/NUMAfig.gif">
<IMG ALIGN=LEFT WIDTH=80 HEIGHT=80 SRC="images/NUMAfig.gif"> 
</A>
<A HREF="numahw/pictures/dbgstn.jpg">
<IMG ALIGN=RIGHT WIDTH=80 HEIGHT=80 SRC="numahw/numa2.gif"> 
</A>
</P>
</TD>
</TABLE>

<P>
<HR WIDTH="100%"></P>

<P>Major funding from:<BR>
<IMG HSPACE=5 VSPACE=5 SRC="images/NSERC.gif" ALIGN=CENTER>
<A HREF="http://www.nserc.ca">Natural Sciences and Engineering Research Council of Canada (NSERC)</A>
</P>

</BODY>
</HTML>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
   <TITLE> Documentation on the NUMAchine Multiprocessor </TITLE>
   <META NAME="GENERATOR" CONTENT="Mozilla/3.0Gold (X11; I; SunOS 5.5 sun4m) [Netscape]">
</HEAD>
<BODY BACKGROUND="images/maple_back.gif">

<CENTER><P><IMG SRC="numahw/NUMAchine-med.gif" > <clear=left><BR>
<BR>
</P></CENTER>

<H2 ALIGN=CENTER>Documentation on the NUMAchine Multiprocessor</H2>

<P>
<HR WIDTH="100%"><BR>
<FONT SIZE=+1>Technical Report</FONT></P>

<P>We have written a technical report that describes the NUMAchine architecture,
outlines important aspects of its cache coherence protocol, and provides
simulation results for parallel execution of a number of benchmark programs.
</P>

<UL>
<LI><A HREF="http://www.eecg.toronto.edu/parallel/parallel/numachin.hier/numachin.html">Hierarchical HTML version of
NUMAchine Technical Report</A><BR>
<BR>
</LI>

<LI><A HREF="http://www.eecg.toronto.edu/parallel/parallel/numachin.flat/numachin.html">Monolithic HTML version of NUMAchine
Technical Report (103 Kbytes)</A><BR>
<BR>
</LI>

<LI><A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/techreport.ps">PostScript version of NUMAchine Technical Report
(451 Kbytes)</A><BR>
<BR>
</LI>

<LI><A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/techreport.pdf">PDF version of NUMAchine Technical Report
(175 Kbytes)</A><BR>
<I><B>Note:  some figures do not come out properly in the PDF.<BR>
Grab the PostScript version instead for now.</B></I></LI>
</UL>

<P>
<HR WIDTH="100%"><BR>
<FONT SIZE=+1>Papers</FONT></P>

<UL>
<li>R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vranesic and Z. Zilic , "The NUMAchine Multiprocessor", <i>Proceedings of the 2000 International Conference on Parallel Processing</i>, Toronto, August 2000.<br>
<a href="http://www.eecg.toronto.edu/parallel/parallel/docs/icpp00.pdf">full paper, (PDF, 109k)</a>
<!--A pdf version of the paper is available in ~grbic/icpp00.pdf. Please make a copy of it in the webpage directory.--> 
<p>

<LI>A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless,
N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic,
&quot;Design and Implementation of the NUMAchine Multiprocessor,&quot;
<I>Proceedings of the 35th IEEE Design Automation Conference</I>,
San Francisco, June 1998.<BR>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/dac98.ps">full paper (PostScript,
160 Kbytes)</A><BR>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/dac98.pdf">full paper (PDF,
41 Kbytes)</A></LI><BR>

<LI>S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley,
M. Gusat, K. Loveless, Z. Zilic, and S. Srbljic, &quot;Experience in Designing
a Large-scale Multiprocessor using Field-Programmable Devices and Advanced
CAD Tools,&quot; <I>Proceedings of the 33rd IEEE Design Automation Conference</I>,
Las Vegas, June 1996.<BR>
<A HREF="http://www.eecg.toronto.edu/~brown/DAC96.html">abstract<BR></A>
<A HREF="http://www.eecg.toronto.edu/~brown/dac96.ps">full paper (PostScript,
177 Kbytes)</A><BR>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/dac96.pdf">full paper (PDF,
63 Kbytes)</A></LI><BR>

<LI>
Z. Zilic, G. Lemieux, K. Loveless, S. Brown, and Z. Vranesic,
&quot;Designing for High Speed-Performance in CPLDs and FPGAs,&quot;
<I>Proc. 3rd Canadian Workshop on Field-Programable
Devices (FPD'95): Technology, Tools, and Applications</I>,
Montreal, Canada, pp. 108 - 113, May 1995.</A><BR>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/fpd95.pdf">
full paper (PDF, 31 Kbytes)</A>
</LI><BR>

<LI>
T. Abdelrahman, S. Brown, T. Mowry, K. Sevcik, M. Stumm, Z. Vranesic, 
S. Zhou, A. Elkateeb, M. Gusat, P. Pereira, B. Gamsa, R. Grindley, O Kreiger, 
G. Lemieux, K. Loveless, N. Manjikian, G. Ravindran, S. Srbljic, Z. Zilic
&quot;An Overview of the NUMAchine Multiprocessor Project,&quot;
<I>Proceedings of the 8th Canadian Supercomputing Conference</I>,
June 1994.</A><BR>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/overview.ps">full paper (PostScript,
224 Kbytes)</A><BR>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/overview.pdf">full paper (PDF,
200 Kbytes)</A></LI><BR>

</LI>

</UL>

<P>
<HR WIDTH="100%"><BR>
<A NAME="systemmanuals">
<FONT SIZE=+1>System Manuals</FONT></P></A>
<P>We are developing the system-level programming documentation to provide
details on the NUMAchine address space and describe various special functions
controlled by system software.</P>

<UL>
<LI><A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/sys_prog_manual.pdf">
NUMAchine Principles of Operations for System Programmers (PDF, 228 Kbytes)<BR>
</A><B><I>DISCLAIMER: this is a preliminary document and is subject to
change at anytime.</I></B></LI>
</UL>

<P> Also, the hardware reference manual describes all of those nitty-gritty details
that the software types don't really care about. Those who work closely
with the hardware should be familiar with this manual.</P>  

<UL>
<LI><A HREF="http://www.eecg.toronto.edu/parallel/parallel/docs/hw_maintenance_manual.pdf">
NUMAchine Hardware Reference and Maintenance Manual (PDF, 539 Kbytes)<BR>
</A><B><I>DISCLAIMER: this is a preliminary document and is subject to
change at anytime.</I></B></LI>
</UL>

<P>
<HR WIDTH="100%"><BR>
<FONT SIZE=+1>NUMAchine-related Theses</FONT></P>
<UL>
The following theses offer greater insight into the
details of the NUMAchine hardware.  However, note that
the content of the theses is dated, and changes to the hardware
have been made for various reasons (integration, economics,
correctness, etc.).  Consequently, the information below
does not accurately document the state of the NUMAchine hardware
as it is today.  Instead, consult either the
<A HREF="http://www.eecg.toronto.edu/parallel/numadocs.html#systemmanuals">
<I>System Programming Manual</I></A>
or
<A HREF="http://www.eecg.toronto.edu/parallel/numadocs.html#systemmanuals">
<I>Hardware Reference and Maintenance Manual</I></A>,
as these will be kept as current as possible.<BR><BR>

<LI>Eddy Ah Pin,
&quot;Hardware Performance Monitoring in Memory of NUMAchine Multiprocessor,&quot;
<I>Undergraduate Thesis,</I> University of Toronto, 1997.
<BR><A HREF="http://www.eecg.toronto.edu/parallel/parallel/theses/ahpin.pdf">PDF, 146k</A></LI><BR>

<LI><A HREF="http://www.eecg.toronto.edu/~grbic">Alex Grbic</A>,
&quot;Hierarchical Directory Controllers in the NUMAchine Multiprocessor,&quot;
<I>M.A.Sc. Thesis,</I> University of Toronto, 1996.
<BR><A HREF="http://www.eecg.toronto.edu/parallel/parallel/theses/grbic.pdf">PDF, 4120k</A></LI><BR>

<LI><A HREF="http://www.eecg.toronto.edu/~grbic">Alex Grbic</A>,
&quot;Assessment of Cache Coherence Protocols in Shared-Memory Multiprocessors,&quot;
<I>Ph.D. Thesis,</I> University of Toronto, 2003.
<BR><A HREF="http://www.eecg.toronto.edu/parallel/parallel/theses/grbic_phd.pdf">PDF, 1064k</A></LI><BR>

<LI><A HREF="http://www.eecg.toronto.edu/~grindley">Robin Grindley</A>,
&quot;The NUMAchine Multiprocessor: Design and Analysis,&quot;
<I>Ph.D. Thesis,</I> University of Toronto, 1999.
<BR><A HREF="http://www.eecg.toronto.edu/parallel/parallel/theses/grindley.pdf">PDF, 1776k</A></LI><BR>

<LI><A HREF="http://www.eecg.toronto.edu/~lemieux">Guy Lemieux</A>,
&quot;Hardware Performance Monitoring in Multiprocessors,&quot;
<I>M.A.Sc. Thesis,</I> University of Toronto, 1996.
<BR><A HREF="http://www.eecg.toronto.edu/parallel/parallel/theses/lemieux.pdf">PDF, 219k</A></LI><BR>

<LI><A HREF="http://www.eecg.toronto.edu/~kelvin">Kelvin Loveless</A>,
&quot;The Implementation of Flexible Interconnect in the NUMAchine Multiprocessor,&quot;
<I>M.A.Sc. Thesis,</I> University of Toronto, 1996.
<BR><A HREF="http://www.eecg.toronto.edu/parallel/parallel/theses/loveless.pdf">PDF, 848k</A></LI><BR>

<li>Karl Schabas, "The Implementation of Basic Monitoring Functions on 
the NUMAchine Multiprocessor", <i>Undergraduate Thesis</i>, 
University of Toronto, 2000.<br>
<a href="http://www.eecg.toronto.edu/parallel/parallel/theses/schabas.pdf">PDF, 281K</A>
<!--   A pdf version of the paper is available in ~grbic/schabas.pdf.  
Also make a copy of it in the webpage directory.--> 
<p>
</UL>
<HR WIDTH="100%"></P>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
   <TITLE>Hardware Development for the NUMAchine Multiprocessor</TITLE>
   <META NAME="GENERATOR" CONTENT="Mozilla/3.0Gold (X11; I; SunOS 4.1.3_U1 sun4m) [Netscape]">
   <META NAME="Author" CONTENT="Naraig Manjikian">
</HEAD>
<BODY background = "../images/maple_back.gif">

<CENTER><P><IMG SRC="NUMAchine-med.gif" HEIGHT=89 WIDTH=502></P></CENTER>

<H2 ALIGN=CENTER>Hardware Development for the NUMAchine Multiprocessor<BR>
at the University of Toronto</H2>

<P>A 64-processor prototype of the <A HREF="../NUMA.Welcome.html">NUMAchine
multiprocessor</A> architecture (illustrated below) is under construction
in the <A HREF="http://www.ece.toronto.edu">Dept. of Electrical /Computer
Engineering</A> at the <A HREF="http://www.toronto.edu">Univ. of Toronto</A>.
</P>

<CENTER><P><IMG SRC="NUMAchine.arch.gif" BORDER=2 HEIGHT=236 WIDTH=548></P></CENTER>

<P>The implementation of each <I><A HREF="numahw.html#station">station</A></I> is
based on the FutureBus+ physical standard, but NUMAchine utilizes a custom
synchronous bus protocol.</P>

<P>A number of printed circuit boards have been designed and fabricated:</P>

<UL>
<LI><I><A HREF="numahw.html#processor board">processor board</A></I> with a MIPS R4400
microprocessor and 1 MByte of SRAM cache<BR>
<BR>
</LI>

<LI><A HREF="numahw.html#memory board"><I>memory board</I> </A>containing 32-128 MBytes
of DRAM and 8 MBytes of SRAM for the cache coherence directory<BR>
<BR>
</LI>

<LI><I><A HREF="numahw.html#network interface board">network interface board</A></I>
to link a station to the ring hierarchy; this board also contains<BR>
8 MBytes of DRAM to cache remote data<BR>
<BR>
</LI>

<LI><A HREF="numahw.html#clock generator board"><I>clock generator</I> </A>generates up
to 18 differential ECL clocks<BR>
<BR>
</LI>

<LI><A HREF="numahw.html#bus arbiter board"><I>bus arbiter</I> </A>a centralized bus
arbiter controls access to the NUMAchine station bus<BR>
<BR>
</LI>

</UL>

<P><B>Status:</B> <EM>The I/O board has been fabricated and is
working... pictures pending.
Also, a number of circuit boards which implement the global ring
for the top level of the interconnection network have been fabricated
and are being tested.</EM></P>

<P>All boards utilize field-programmable devices (FPDs) from the <A HREF="http://www.altera.com">Altera
Corporation</A> for much of the control circuitry, such as the system interface
for the <A HREF="http://www.mips.com">MIPS R4400 microprocessor</A>, the
directory controller on the memory board, and the ring controller on the
network interface board. Field-programmable devices provide shorter design
cycles and cost-effectiveness (although good performance requires <A HREF="http://www.eecg.toronto.edu/~brown/DAC96.html">careful
design</A>). In addition, FPDs provide flexibility to implement new protocols
to support future research.<BR>
<BR>
<BR>
<BR>
</P>

<CENTER><P><B><I>The NUMAchine Hardware Development Group</I></B> </P></CENTER>

<CENTER><TABLE CELLSPACING=20 CELLPADDING=0 >
<TR>
<TD VALIGN=TOP>
<LI>Prof. Zvonko G. Vranesic (<I>project leader</I>)</LI>

<LI>Prof. Stephen D. Brown</LI>

<LI>Prof. Michael Stumm</LI>

<LI>Steve Caranci</LI>

<LI>Alex Grbic</LI>

<LI>Guy Lemieux</LI>

<LI>Paul McHardy</LI>

<LI>Peter Pereira</LI>


</TD>

<TD VALIGN=TOP>Major contributors who have moved on: 
<LI>Dr. Robin Grindley</LI>
<LI>Mitch Gusat</LI>
<LI>Dr. Orran Krieger</LI>
<LI>Kelvin Loveless</LI>
<LI>Dr. Naraig Manjikian</LI>
<LI>Dr. Sinisa Srbljic</LI>
<LI>Michael van Dam</LI>
<LI>Dr. Zeljko Zilic</LI>

<P>Summer students:</P>
<LI>Eddy Ah Pin</LI>
<LI>Terry Borer</LI>
<LI>Jackson Fung</LI>
<LI>Emanuel Istrate</LI>
<LI>Daniel Levner</LI>
<LI>Karl Schabas</LI>
<LI>Deshanand P. Singh</LI>
</TD>
</TR>
</TABLE></CENTER>

<P>
<HR WIDTH="100%"></P>

<H2>Photographs of NUMAchine Hardware</H2>

<P><A NAME="station"></A></P>

<TABLE BORDER=1 CELLPADDING=10 >
<TR>
<TD>
<A HREF="pictures/dbgstn.jpg">
<IMG SRC="numa2.gif" HEIGHT=225 WIDTH=262 ALIGN=TEXTTOP></A></TD>

<TD>
<CENTER><P><B><I><FONT SIZE=+1>A Fully-populated<BR>
NUMAchine Station</FONT></I></B></P></CENTER>

<P>The bus physical backplane is at the bottom of the photograph. The boards
plug vertically into the backplane.</P>

<P>From left to right:</P>

<LI>bus arbiter board</LI>

<LI>4 processor boards</LI>

<LI>2 memory boards</LI>

<LI>network interface board</LI>

<P>The power supply is visible directly beneath the bus backplane. A clock
generation and distribution board (not visible) is located underneath the
backplane.</P>
</TD>
</TR>
</TABLE>

<P><A NAME="processor board"></A></P>

<TABLE BORDER=1 CELLPADDING=10 >
<TR>
<TD>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/pictures/proc.jpg">
<IMG SRC="proc.gif" HEIGHT=378 WIDTH=308 ALIGN=TEXTTOP></A></TD>

<TD>
<CENTER><P><B><I><FONT SIZE=+1>The Processor Board</FONT></I></B></P></CENTER>

<P>At the top of the board are LED displays and connectors for diagnostics,
EPROM to program the Altera FPDs, and EPROM with boot code for the R4400.</P>

<P>The MIPS R4400 microprocessor with heat sink is at the center of the
board, surrounded by SRAM cache chips.</P>

<P>Directly below the R4400 is a row of Altera field-programmable devices
which serve as the system interface for the R4400. Below these chips is
a row of FIFO buffers to and from the NUMAchine station bus. Finally, below
the FIFOs is a row of FutureBus+ BTL chips for listening to and driving
the NUMAchine station bus.</P>

<P>Click on the picture to see the latest version of the processor board,
revision 3, in detail.</P>

<P>The connector to the NUMAchine station bus is at the bottom of the board.</P>
<P><A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/procr.pic.ps">Block diagram (PostScript, 95 Kbytes)</A><P>
</TD>
</TR>
</TABLE>

<P><A NAME="memory board"></A></P>

<TABLE BORDER=1 CELLPADDING=10 >
<TR>
<TD>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/pictures/mem.jpg">
<IMG SRC="mem.gif" HEIGHT=450 WIDTH=450 ALIGN=TEXTTOP></A></TD>

<TD>
<CENTER><P><B><I><FONT SIZE=+1>The Memory Board</FONT></I></B></P></CENTER>

<P>DRAM SIMMs occupy the left side of the board. The top right-hand corner
is occupied by a bank of SRAM chips used in maintaining the directory for
the cache coherence protocol. </P>

<P>At the right-hand center of the board are the Altera FPDs which contain
the control circuitry for the cache coherence protocol. There is also an
Altera FPD at the top center of the board to control the DRAM array.</P>

<P>FIFO buffers and BTL interface chips connect the memory board to the
NUMAchine station bus through the connector at the bottom of the board.</P>

<P>Click on the picture to see the latest version of the memory board,
revision 2, in detail.  Hardware monitoring, which was not present in
the original revision, has been added in the Altera FLEX10K30 device.
The patchwires were necessary to correct an FPGA programming problem,
and have been eliminated with a final respin of the board.</P>

<P><A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/mem.pic.ps">Block diagram (PostScript, 99 Kbytes)</A><P>
</TD>
</TR>
</TABLE>

<P><A NAME="network interface board"></A></P>

<TABLE BORDER=1 CELLPADDING=10 >
<TR>
<TD>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/pictures/nic.jpg">
<IMG SRC="ni.gif" HEIGHT=445 WIDTH=313 ALIGN=TEXTTOP></A></TD>

<TD>
<CENTER><P><B><I><FONT SIZE=+1>The Network Interface Board</FONT></I></B></P></CENTER>

<P>The ring connectors are visible in the top corners of the board. The
buffers for the ring interconnect occupy the space between the connectors.</P>

<P>The DRAM chips for the remote data cache occupy a small area on the
underside of the board.</P>

<P>The Altera FPDs containing the control circuitry for the cache coherence
protocol, the rings, and the remote data cache are clearly visible in their
sockets.</P>

<P>Pipelining for the wide data paths on this board requires the large
number of buffer chips which occupy much of the board.</P>

<P>FIFO buffers and BTL chips are located at the bottom left and bottom
right, as well as the the bottom edge of the board, directly above the
connector to the NUMAchine station bus.</P>

<P>Click on the picture to see the latest version of the network interface
board, revision 2, in detail.  You will notice that many of the discrete
buffers have been replaced with Altera FLEX6016 FPGAs.  Also, the SDRAM
has been moved to the top surface.</P>

<P><A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/ni.pic.ps">Block diagram (PostScript, 97 Kbytes)</A><P>
</TD>
</TR>
</TABLE>

<P><A NAME="clock generator board"></A></P>

<TABLE BORDER=1 CELLPADDING=10 >
<TR>
<TD>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/pictures/clock.jpg">
<IMG SRC="pictures/clock_small.jpg" WIDTH=200 ALIGN=TEXTTOP></A></TD>

<TD>
<CENTER><P><B><I><FONT SIZE=+1>The Clock Generator Board</FONT></I></B></P></CENTER>

<P>The clock generator board can be programmed to a wide range of
frequencies by the red DIP switch block.  Differential the ECL master
clock is generated by the chip in the top, centre of the board and
split 2:1 by the small chip in the centre.  The left and right chips
are 9:1 fanout replicators, giving a total of 18 ECL clock signals.
We distribute the clocks to the NUMAchine backplane via twisted-pair
cables.  Of course, we must take care that the cables are all the
same length to minimize skew mismatch between the signals.</P>
</TD>
</TR>
</TABLE>

<P><A NAME="bus arbiter board"></A></P>

<TABLE BORDER=1 CELLPADDING=10 >
<TR>
<TD>
<A HREF="http://www.eecg.toronto.edu/parallel/parallel/numahw/pictures/arb.jpg">
<IMG SRC="pictures/arb_small.jpg" WIDTH=300 ALIGN=TEXTTOP></A></TD>

<TD>
<CENTER><P><B><I><FONT SIZE=+1>The Bus Arbiter Board</FONT></I></B></P></CENTER>

<P>The bus arbiter board is a centralized, synchronous arbiter that
controls access to the NUMAchine bus.  Since this was one of the first
boards we made, a few miscellaneous test circuits were also added to
experiment with high-speed signalling using Altera devices.  These test
circuits use the DIP switches to test different functions.  Also, a
NUMAchine station RESET switch is located on this board, just below the
DIP switches.</P>

<P>The bus arbiter function has been added to the latest version
of the I/O Board.  Unfortunately, we do not have scans of that board
ready yet for display.</P>

</TD>
</TR>
</TABLE>





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<!-- RCS $Id: projects.html,v 1.3 1994/11/02 20:30:13 caranci Exp caranci -->
<HTML>
<body bgcolor="#ffffff" text="#000000"  link="#0000ff" vlink="#aaaaff" alink="#0077FF"> </body>
<FONT SIZE=4>

<HEAD>
<TITLE>Current UofT EECG Projects</TITLE>
</HEAD>

<BODY>
<H1>Current Projects</H1>

<DL>

<DT><a href="hector.html">
Hector</A>
<DD>Hector is a scalable shared memory multiprocessor with an 
interconnect of hierachical rings.

<DT><a href="hurricane.html">
Hurricane</A>
<DD>
Hurricane is a hierarchically clustered operating system implemented on the
Hector multiprocessor. 

<DT><a href="numachine.html">
<IMG SRC="images/NUMAchine-small.gif" ALT = "NUMAchine"></A>
<DD>
<A href="numachine.html">NUMAchine</A>
is a next-generation implemenation of the basic Hector 
multi-processor architecture.
Features include: 
  hardware cache-coherency, 
  network cache (a lockup-free tertiary cache), 
  efficient multicast mechanism, and
  hardware performance monitoring support.

<DT><a href="tornado.html">
<IMG SRC="images/torn-small.gif" border=0 vspace=5 hspace=5 ALT = "Tornado"></A>
</A>
<DD>
<A href="tornado.html">Tornado</A> 
is the operating system being implemented for the NUMAchine
multiprocessor.
It is a multiuser, NUMA-aware, performance-oriented microkernel 
operating system.
Most services are provided by servers and application-level run-time libraries. 
Tornado has a highly modular structure and is implemented in C++.
</DL>

<HR>
<STRONG>This is still a work in progress...<BR>
Please forward any comments, suggestions or questions to:</STRONG><BR>
<a href="mailto:caranci@eecg.toronto.edu"><i>caranci@eecg.toronto.edu</i></a>

</BODY>
</HTML>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
  <head>
    <title>K42/Tornado Web Page Redirection</title>
    <META HTTP-EQUIV="Refresh"
     CONTENT="1; URL=http://www.eecg.toronto.edu/~tornado">
  </head>

  <body>
    <h1>K42/Tornado Web Page Redirection</h1>
    <p>
    The University of Toronto K42/Tornado web page has moved to
<a href="http://www.eecg.toronto.edu/~tornado/">http://www.eecg.toronto.edu/~tornado/</a>.
    If your browser doesn't automatically redirect to its new location,
    click the above link.
    </p>

    <hr>
    <address><a href="mailto:tamda@eecg.toronto.edu">David Kar-Fai Tam</a></address>
<!-- Created: Tue Oct  7 17:23:32 EDT 2003 -->
<!-- hhmts start -->
Last modified: Tue Oct  7 17:36:05 EDT 2003
<!-- hhmts end -->
  </body>
</html>

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<HTML>
<body bgcolor="#ffffff" text="#000000"  link="#0000ff" vlink="#aaaaff" alink="#0077FF"> </body>
<FONT SIZE=4>
<HEAD>
<TITLE>People</TITLE>
<!-- Changed by: Orran Y. Krieger, 18-Apr-1996 -->
</HEAD>
<center>
<H1>
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/music1.gif"></A>
<P>
People</H1>
</center>
<BODY>

<img align=left src="images/comments.gif"> 
Please mail changes and additions to
<A HREF="mailto:kulki@cs.toronto.edu">Kulki</A> or 
<A HREF="mailto:okrieg@eecg.toronto.edu">Orran</A>  
 <p>
<br>

<H2>Faculty</H2>
<UL>
<LI> <A href="http://www.eecg.toronto.edu/~tsa/Welcome.html">T. Abdelrahman</a>
<LI> <A href="../~brown/Welcome.html">S. Brown </a>
<LI> <A href="../~corinna.html">C. Lee </a>
<LI> <A href="http://www.eecg.toronto.edu/~tcm/Welcome.html">T. Mowry </a>
<LI> <A href="http://www.cs.toronto.edu/~kcs">K. Sevcik </a>
<LI> <A href="../~stumm/Welcome.html">M. Stumm </a>
<LI> <A href="../~zvonko/Welcome.html">Z. Vranesic </a>
<LI> <A href="http://www.eecg.toronto.edu/~zhou/Welcome.html">S. Zhou </a>
</UL>
<P>

<H2>Students</H2>
<UL>
<LI> <A href="http://www.eecg.toronto.edu/~bernecky">R. Bernecky</a>
<LI> <A href="../~charlesc.html">C. Chan</a>
<LI> <A href="http://www.eecg.toronto.edu/~demke">A. Demke</a>
<LI> <A href="http://www.eecg.toronto.edu/~devrier">D. De Vries</a>
<LI> <A href="../~dunc/index.html">D. Elliott</a>
<LI> <A href="http://www.eecg.toronto.edu/~farkas/">K. Farkas</a>

<LI> <A href="../~ben/Welcome.html">B. Gamsa </a>
<LI> <A href="http://www.eecg.toronto.edu/~grindley/Welcome.html">R. Grindley </a>

<LI> <A href="http://www.eecg.toronto.edu/~grbic">A. Grbic </a>

<LI> <A href="http://www.eecg.toronto.edu/~gusat">R. Ho </a>
<LI> <A href="http://www.eecg.toronto.edu/~shuynh/va/Welcome.html">S. Huynh </a>
<LI> <A href="http://www.eecg.toronto.edu/~hora/Welcome.html">M. Gusat </a>
<LI> <A href="http://www.cs.toronto.edu/~karim">K. Harzallah</a>
<LI> <A href="http://www.eecg.toronto.edu/~jaseemud">M. Jaseemuddin</a>
<LI> <A href="http://www.cs.toronto.edu/~kulki">D. Kulkarni</a>
<LI> <A href="http://www.cs.toronto.edu/~lamma">M. Lam</a>
<LI> <A href="http://www.eecg.toronto.edu/~lemieux/Welcome.html">G. Lemieux </a>
<LI> <A href="http://www.cs.toronto.edu/~paullu">P. Lu</A>
<LI> <A href="http://www.cs.toronto.edu/~luk">C. Luk</A>
<LI> <A href="http://www.eecg.toronto.edu/~kma">K. Ma </a>
<LI> <A href="http://www.cs.toronto.edu/~maione">I. Maione </a>
<LI> <A href="http://www.eecg.toronto.edu/~nmanjiki/Welcome.html">N. Manjikian </a>
<LI> <A href="http://www.cs.toronto.edu/~neto">D. Neto </a>
<LI> <A href="http://www.cs.toronto.edu/~eparsons">E. Parsons</A>
<LI> <A href="http://www.cs.toronto.edu/~phan">G. Phan</A>
<LI> <A href="http://www.eecg.toronto.edu/~gravin/Welcome.html">G. Ravindran </a>
<LI> <A href="http://www.eecg.toronto.edu/~reid/Welcome.html">K. Reid</A>
<LI> <A href="http://www.eecg.toronto.edu/~reza">R. Solymaani</A>
<LI> <A href="../~saghir.html">M. Saghir</A>
<LI> <A href="../~steffan.html">G. Steffan</A>
<LI> <A href="http://www.eecg.toronto.edu/~stoodla">M. Stoodley</A>
<LI> <A href="http://www.eecg.toronto.edu/~tandri/Welcome.html">S. Tandri</a>
<LI> <A href="http://www.eecg.toronto.edu/~zeljko/Welcome.html">Z. Zilic </a>
</UL>
<P>

<H2>Staff</H2>
<UL>
<LI> <A href="http://www.eecg.toronto.edu/~caranci/Welcome.html">S. Caranci</A>
<LI> <A href="http://www.eecg.toronto.edu/~okrieg/Welcome.html">O. Krieger </a>
<LI> <A href="http://www.eecg.toronto.edu/~kelvin/Welcome.html">K. Loveless </a>
<LI> <A href="../~peterp/Welcome.html">P. Pereira </a>
</UL>

<H2>Graduates</H2>
<UL>
<LI> <A href="http://www.cs.ualberta.ca/~unrau">R. Unrau</A>
<LI> <A href="http://www.cs.yorku.ca/People/brecht">T. Brecht</A>
<LI> <A href="http://www.eecg.toronto.edu/~okrieg/Welcome.html">O. Krieger </a>
<LI> <A href="http://www.cs.yorku.ca/People/hsandhu">H. Sandhu</A>
<LI> <A href="http://www.eecg.toronto.edu/~hui">H. Li</A>
</UL>

<A HREF="Welcome.html"> <img align="left" src="images/homeblue.gif"> Return to Parallel Systems Home </A>

</BODY>
</HTML>

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<TITLE>Publications</TITLE>
<A NAME="BEG"> </A>
<!-- Changed by: Orran Y. Krieger, 12-Nov-1995 -->
<body bgcolor="#ffffff" text="#000000"  link="#0000ff" vlink="#aaaaff" alink="#0077FF"> </body>
<FONT SIZE=4>
<BR>
<center>
<H1>
<img align="left" src="../EECG/RESEARCH/ParallelSys/images/journal.gif">
Publications</H1>
</center>
<BR>
<BR>
<P>

Most of these papers can also be
<A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel">accessed via ftp</A>.
A full, un-sorted,
<A HREF="pubs_abs.html">list of publications with abstracts</A>
is also available.
<P>
<em>
<img align="left" src="../EECG/RESEARCH/ParallelSys/images/comments.gif"><A HREF="mailto:kulki@cs.toronto.edu"> Please send your suggestions and comments.</A>
<p>
<BR>
<em>
Group members: 
Whenever you have a paper for public eyes 
please mail <strong> kulki@eecg.toronto.edu </strong> a
text with author and source information, text abstract, and a postscript file
with embedded source information.
</em>
<P>
<BR>
<BR>
<BR>

<center>
<A HREF="publications.html#ca">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/arch_button.gif"></A>
<P>
<A HREF="publications.html#os">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/os_button.gif"></A>
<P>
<A HREF="publications.html#compilers">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/comp_button.gif"></A>
<P>
<A HREF="publications.html#scheduling">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/sch_button.gif"></A>
<P>
<A HREF="publications.html#pe">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/perf_button.gif"></A>
<P>
<A HREF="publications.html#db">
<img align="center" src="../EECG/RESEARCH/ParallelSys/images/data_button.gif"></A>
</center>
<P>
<BR>
<BR>
<BR>
<BR>
<BR>
<P>
<A HREF="Welcome.html"> <img align="left" src="images/homeblue.gif"> Return to Parallel Systems Home </A>
<P>
<img src="images/redline.GIF"> <p>

<A NAME="ca"><H2>Computer Architecture</H2></A>
<UL>
<LI>  <A HREF="pubs_abs.html#Ravi_Stumm_JIEICE96">
A Comparison of Blocking and Non-blocking Packet Switching
        Techniques in Hierarchical Ring Networks </A>
<br>
 IEICE Trans 1996
<LI>  <A HREF="pubs_abs.html#Ravi_Stumm_ICPP95">
Hierarchical Ring Topologies and the effect of their Bisection
       Bandwidth Constraints </A> 
<br>
ICPP 1995
<LI>  <A HREF="pubs_abs.html#Wilton_Vranesic_SPDP">Architectural Support for Block Transfers in a Shared-Memory Multiprocessor</A>
<br> SPDP 1993
<LI>  <A HREF="pubs_abs.html#Stumm_Vranesic_White_IPPS93">Experience with the Hector Multiprocessor</A>
<br> IPPS 1993
<LI>  <A HREF="pubs_abs.html#Vranesic_etal_IEEEC">Hector -- A hierarchically
structured shared memory multiprocessor</A>
<br> IEEE Computer 1991
<LI>  <A HREF="pubs_abs.html#Holliday_Stumm_IEEETC">Performance Evaluation of Hierarchical Ring-Based Shared Memory Multiprocessors </A> 
<br> IEEE Trans. Computer 1992
</UL>

<P>
<A HREF="publications.html#BEG" > Return to the LIST</A>
<P>

<img src="images/redline.GIF"> <p>

<A NAME="os"><H2>Operating Systems</H2></A>
<UL>

<LI>  <A HREF="pubs_abs.html#Orran_etal_SPDPW95">
Exploiting Mapped Files for Parallel I/O
</A> <br> 1995 SPDP Workshop on Modeling and Specification of I/O (MSIO) 
<LI>  <A HREF="pubs_abs.html#Parsons_etal_IWOOS95">(De-)Clustering Objects for Multiprocessor System Software </A> 
<br>   
IWOOS95 Workshop 
<LI>  <A HREF="pubs_abs.html#Unrau_etal_EuroPar95">On the Scalability of Demand-Driven Parallel Systems</A> 
<br> EuroPar 95
<LI>  <A HREF="pubs_abs.html#Ben_etal_OOPSLAW94">The Importance of Performance-Oriented Flexibility in System Software for Large-Scale Shared-Memory Multiprocessors </A> <br>  OOPSLA 94 Workshop on Flexible System Software 
<LI>
<A HREF="pubs_abs.html#Unrau_etal_OSDI94"> Experiences  with Locking in a NUMA Multiprocessor Operating System Kernel </A> <br>  
OSDI 1994
<LI>
<A HREF="pubs_abs.html#Unrau_etal_JSC94">Hierarchical clustering: A structure for scalable multiprocessor operating system design</A> <br> 
Journal of Supercomputing 1995
<LI>  <A HREF="pubs_abs.html#Okrieg_PhD">HFS: A flexible file system for shared-memory multiprocessors</A> <br>  
PhD thesis, 1994
<LI>  <A HREF="pubs_abs.html#Krieger_etal_IEEEComp94">The Alloc Stream Facility: A redesign of application-level Stream I/O</A> <br> 
IEEE Computer 1994
<LI>  <A HREF="pubs_abs.html#Gamsa_etal_ICPP94">Optimizing IPC Performance for Shared-Memory Multiprocessors</A> <br>  
ICPP 1994
<LI>  <A HREF="pubs_abs.html#Sandhu_et_al_PPOPP">The shared  regions  approach to software cache coherence on multiprocessors</A> <br>  
PPoPP 1993
<LI>  <A HREF="pubs_abs.html#Krieger_Stumm_DAGS93">HFS: A Flexible File System for Large-Scale Multiprocessors</A> <br> 
DAGS 1993
<LI>  <A HREF="pubs_abs.html#Krieger_etal_ICPP93">A Fair Fast Scalable Reader-Writer Lock</A> <br> 
ICPP 1993
<LI>  <A HREF="pubs_abs.html#Stumm_Unrau_Krieger_USENIX92">Hierarchical Clustering: A Structure for Scalable Multiprocessor Operating System Design</A> <br> 
USENIX 1992
<LI>  <A HREF="pubs_abs.html#Gamsa_MASc">Region-Oriented Main Memory Management in Shared-Memory NUMA Multiprocessors</A> <br> 
MASc thesis, 1992
<LI>  <A HREF="pubs_abs.html#Unrau_PhD">Scalable Memory Management through Hierarchical Symmetric Multiprocessing</A> <br>  
PhD thesis, 1992

</UL>
<P>
<A HREF="publications.html#BEG" > Return to the LIST</A>
<P>

<img src="images/redline.GIF"> <p>

<A NAME="compilers"><H2>Compilers</H2></A>
<UL>
<LI>  <A HREF="pubs_abs.html#Tandri_Abdel_PDPTA95">Computation and Data Partitioning on Scalable Shared Memory Multiprocessors</A> PDPTA, November 1995 
<LI>  <A HREF="pubs_abs.html#Kulkarni_Stumm_Tut">Loop and Data Transformations:Tutorial</A> CSRI Tech Report 337, June 1993
<LI>  <A HREF="pubs_abs.html#Li_Tandri_et">Locality and Loop Scheduling on Numa Multiprocessors</A>
<br> ICPP 92
<LI>  <A HREF="pubs_abs.html#Manjikian_Abdelrahaman_315">Fusion of Loops for Parallelism and Locality</A> 
<br> Tech Report
<LI>  <A HREF="pubs_abs.html#Kulkarni_Stumm_LCR95">CDA Loop Transformations</A> 
<br> 3rd LCR Workshop
<LI>  <A HREF="pubs_abs.html#Kulkarni_Stumm_Unrau_EuroPar95">Implementing Flexible Computation Rules with Subexpression-level Loop Transformations</A> 
<br> EuroPar 95
<LI>  <A HREF="pubs_abs.html#Kulkarni_etal_317">A Generalized Theory of Linear Loop Transformations</A> 
<br> Tech Report
<LI>  <A HREF="pubs_abs.html#Kulkarni_Stumm_292">Computational Alignment: A new, unified program transformation for local and global optimization</A> 
<br> Tech Report
<LI>  <A HREF="pubs_abs.html#Kulkarni_Stumm_ACJ95">Linear Loop Transformations in Optimizing Compilers for Parallel Machines</A> 
<br> Australian Computer Journal
<LI>  <A HREF="pubs_abs.html#Kumar_Kulkarni_ICS92">Deriving Good Transformations for Mapping Nested Loops on Hierarchical Parallel Machines in Polynomial Time</A>
<br> ICS 92
<LI>  <A HREF="pubs_abs.html#Kumar_Kulkarni_ICPP91">Generalized Unimodular Loop Transformations for Distributed Memory Multiprocessors</A> (does not contain figures)
<br> ICPP 91
</UL>
<P>
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<P>


<img src="images/redline.GIF"> <p>

<A NAME="scheduling"><H2>Scheduling</H2></A>
<UL>
<LI>  <A HREF="pubs_abs.html#Zhou_Brecht_SM91">Processor Pool-Based Scheduling for Large-Scale NUMA Multiprocessors</A>
<br> Sigmetrics 91
<LI>  <A HREF="pubs_abs.html#Brecht_SEDMS93">On the Importance of Parallel Application Placement in NUMA Multiprocessors</A>
<br> SEDM 93
<LI>  <A HREF="pubs_abs.html#Sevcik_JPE">Application Scheduling and Processor Allocation in Multiprogrammed Parallel Processing Systems</A>
<br> (Journal of) Performance Evaluation 94
<LI>  <A HREF="pubs_abs.html#Curran_Stumm_CS">A Comparison of basic CPU Scheduling Algorithms for Multiprocessor Unix</A> 
<br> (Journal) Computer Systems 90
<LI>  <A HREF="pubs_abs.html#Brecht_PhD_303">Multiprogrammed Parallel Application Scheduling in NUMA Multiprocessors</A>
<br> PhD thesis
<LI>  <A HREF="pubs_abs.html#Wu_MASc">Processor Scheduling in Multiprogrammed Shared Memory NUMA Multiprocessors</A> 
</UL>
<P>
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<P>

<img src="images/redline.GIF"> <p>

<A NAME="pe"><H2>Performance Evaluation</H2></A>
<UL>
<LI>  <A HREF="pubs_abs.html#Sevcik_Zhou_PERF93">Performance Benefits and Limitations of Large NUMA Multiprocessors</A>
<br> Performance 93
<LI>  <A HREF="pubs_abs.html#Harz_Sevcik_SC93">Hot Spot Analysis in Large Scale Shared Memory Multiprocessors</A>
<br> Supercomputing 93
<LI>  <A HREF="pubs_abs.html#Holliday_Stumm_IEEETC">Performance Evaluation of Hierarchical Ring-Based Shared Memory Multiprocessors </A> 
<br> IEEE Trans. Computer 1992 
<LI>  <A HREF="pubs_abs.html#Parsons_Sevcik_IPPS95">Multiprocessor Scheduling for High-Variability Service Time Distributions
</A
<br> IPPS Workshop on Job Scheduling 95
</UL>
<P>
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<P>

<img src="images/redline.GIF"> <p>

<A NAME="db"><H2>Database Systems</H2></A>
<UL>
<LI>  <A HREF="pubs_abs.html#Baru_Zilio_PADS93">Data reorganization in parallel database systems</A>
<br> IEEE Workshop PADS 93
</UL>
<P>
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<P>

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Added wiki_references/2017/software/eecg_toronto_edu/2017_05_12_wget_copy_of_http_www_eecg_toronto_edu_parallel_publications_html/bonnet/www.eecg.toronto.edu/parallel/pubs_abs.html version [aa83589fa9].



















































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































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<!--------------------------------------------------------------------->
<HR><A NAME="Ravi_Stumm_JIEICE96">.</A><HR>
<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Ravi_Stumm_JIEICE96.ps.Z">
A Comparison of Blocking and Non-blocking Packet Switching
        Techniques in Hierarchical Ring Networks

       </A>
 <P>
<B>Authors:</B>  G. Ravindran and M. Stumm
 
 <P>
<B>Where:</B> 
IEICE Trans. Inf. & Syst., vol. E79-D, No. 8, August 1996
<P>
<B>Keywords:</B> 
Networks, Switching, Wormhole, Virtual Cut-through, Hierarchical Ring Networks,
Slotted Rings
<P>
<B>Abstract:</B>
This paper presents the results of a simulation study of blocking and
non-blocking switching for hierarchical ring networks.
The switching techniques include wormhole, virtual cut-through, and
slotted ring.
We conclude that slotted ring network performs better than
the more popular wormhole and virtual cut-through networks.
We also show that the size of the node buffers is an important parameter and
that choosing them too large can hurt performance in some cases.
Slotted rings have the advantage that the choice of buffer size is easier in
that larger than necessary buffers do not hurt performance and hence a single
choice of buffer size performs well for all system configurations.
In contrast, the optimal buffer size for virtual cut-through and wormhole
switching nodes varies depending on the system configuration and the level
in the hierarchy in which the switching node lies.

<P>

<!--------------------------------------------------------------------->
<HR><A NAME="Ravi_Stumm_ICPP95">.</A><HR>
<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Ravi_Stumm_ICPP95.ps.Z">
Hierarchical Ring Topologies and the effect of their Bisection
       Bandwidth Constraints</A>
 <P>
<B>Authors:</B>  G. Ravindran and M. Stumm
 
 <P>
<B>Where:</B> 
 Proc. Intl. Conf. on Parallel Processing, pp.I/51-55, 1995
<P>
<B>Keywords:</B> 
 Multiprocessor architectures, Interconnection networks,
          Hierarchical rings, Bisection bandwidth
<P>
<B>Abstract:</B>

Ring-based hierarchical networks are interesting alternatives to
popular direct networks such as 2D meshes or tori. They allow for
simple router designs, wider communications paths, and faster networks
than their direct network counterparts. However, they have a constant
bisection bandwidth, regardless of system size. In this paper, we
present the results of a simulation study to determine how large
hierarchical ring networks can become before their performance
deteriorates due to their bisection bandwidth constraint. We show that
a system with a maximum of 128 processors can sustain most memory
access behaviors, but that larger systems can be sustained, only if
their bisection bandwidth is increased.

 <P>
<!--------------------------------------------------------------------->
<HR><A NAME="Zhou_Brecht_SM91">.</A><HR>
<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Zhou_Brecht_SM91.ps.Z">Processor Pool-Based Scheduling for Large-Scale NUMA Multiprocessors</A>
 <P>
<B>Authors:</B> Songnian Zhou and Timothy Brecht
 <P>
<B>Where:</B> Appears in: Proceedings of  the  1991  ACM  SIGMETRICS
Conference  on Measurement and Modeling of Computer Systems, May (1991),
pp. 133-142. 
 <P>
<B>Keywords:</B> NUMA, Schedulling, multiprocessor performance
 <P>
<B>Abstract:</B>
 <P>
Large-scale  Non-Uniform  Memory  Access  (NUMA)  multiprocessors  are
gaining  increased attention due to their potential for achieving high
performance through the replication of relatively  simple  components.
Because  of  the complexity of such systems, scheduling algorithms for
parallel  applications  are  crucial  in  realizing  the   performance
potential  of  these  systems.  In particular, scheduling methods must
consider the scale of the system, with  the  increased  likelihood  of
creating  bottlenecks,  along  with  the  NUMA  characteristics of the
system, and the benefits to be gained  by  placing  threads  close  to
their code and data.
 <P>
We propose a class of scheduling algorithms based on processor  pools.
A processor pool is a software construct for organizing and managing a
large number of processors by dividing them into groups called  pools.
The  parallel  threads  of  a  job are run in a single processor pool,
unless there are performance advantages for a  job  to  span  multiple
pools.   Several  jobs may share one pool.  Our simulation experiments
show that processor pool-based scheduling may effectively  reduce  the
average  job  response time.  The performance improvements attained by
using processor pools increase with the  average  parallelism  of  the
jobs, the load level of the system, the differentials in memory access
costs, and the likelihood of having system bottlenecks.  As the system
size   increases,  while  maintaining  the  workload  composition  and
intensity, we observed that processor pools can  be  used  to  provide
significant  performance  improvements.   We  therefore  conclude that
processor pool-based scheduling may  be  an  effective  and  efficient
technique for scalable systems.


<!--------------------------------------------------------------------->

<HR><A NAME="Brecht_SEDMS93">.</A><HR>
<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Brecht_SEDMS93.ps.Z">On the Importance of Parallel Application Placement in NUMA Multiprocessors</A>
 <P>
<B>Authors:</B> Timothy Brecht
 <P>
<B>Where:</B> Proceedings of the Fourth Symposium on Experiences  with
Distributed  and  Multiprocessor  Systems  (SEDMS  IV), San Diego, CA,
September, 1993.
 <P>
<B>Keywords:</B> NUMA, multiprocessor scheduling, multiprocessor performance
 <P>
<B>Abstract:</B>
 <P>
The thesis of this paper is that scheduling decisions in  large-scale,
shared-memory,  NUMA  (Non-Uniform Memory Access) multiprocessors must
consider not only how many processors, but also  which  processors  to
allocate  to  each  application.   We  call  the  problem of assigning
parallel  processes  of  an  application  to  processors   application
placement.
 <P>
We explore the importance of  placement  decisions  by  measuring  the
execution  time  of  several  parallel  applications  using  different
placements on a shared-memory NUMA  multiprocessor.   The  results  of
these  experiments  lead  us  to conclude that, as expected, in small-
scale mildly NUMA multiprocessors, placement  decisions  have  only  a
minor affect on the execution time of parallel applications.  However,
the  results  also  show  that  placement  decisions  in   large-scale
multiprocessors  are  critical  and  localization  that  considers the
architectural clusters inherent in these systems  is  essential.   Our
experiments  also  show  that  the  importance  of placement decisions
increases substantially with the size and NUMAness of the  system  and
that  the  placement  of individual processes of an application within
the  subset  of   chosen   processors   also   significantly   impacts
performance.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Kumar_Kulkarni_ICPP91">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Kumar_Kulkarni_ICPP91.ps.Z">Generalized Unimodular Loop Transformations for Distributed Memory Multiprocessors</A> (does not contain figures)
 <P>
<B>Authors:</B> K G Kumar*, D Kulkarni+ and A Basu
<BLOCKQUOTE>
        Center for Development of Advanced Computing
        2/1 Brunton Road, Bangalore 560 025, India<BR>
* Now at IBM TJ Watson, York Town Heights, NY 10598<BR>
+ Now at Dept of Computer Science, University of Toronto,
         Toronto, ON M5S 1A4<BR>
</BLOCKQUOTE>
 <P>
<B>Where:</B> International Conference of Parallel Processing -91
 <P>
<B>Keywords:</B> Parallelizing Compilers, Restructuring Transformations,
Loop Partitioning, Iteration Spaces, Dependence Vectors. 
 <P>
<B>Abstract:</B>
 <P>
In this paper, we present a generalized unimodular loop
transformation as a simple, systematic and elegant method
for partitioning the iteration spaces of nested loops for
execution on distributed memory multiprocessors. We present
a methodology for deriving the transformations that internalize
multiple dependences in a multidimensional iteration space
without resulting in a deadlocking situation. We then
derive the general expression for the bounds of the
transformed loops in terms of the bounds of the original
space and the transformation matrix elements.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Kumar_Kulkarni_ICS92">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Kumar_Kulkarni_ICS92.ps.Z">Deriving Good Transformations for Mapping Nested Loops on Hierarchical Parallel Machines in Polynomial Time</A>
 <P>
<B>Authors:</B> K G Kumar*, D Kulkarni+ and A Basu
<BLOCKQUOTE>
        Center for Development of Advanced Computing
        2/1 Brunton Road, Bangalore 560 025, India<BR>
* Now at IBM TJ Watson, York Town Heights, NY 10598<BR>
+ Now at Dept of Computer Science, University of Toronto,
         Toronto, ON M5S 1A4<BR>
</BLOCKQUOTE>
 <P>
<B>Where:</B> International Conference on Supercomputing 92
 <P>
<B>Keywords:</B> Parallelizing Compilers, Restructuring Transformations,
Loop Partitioning, Iteration Spaces, Dependence Vectors.
 <P>
<B>Abstract:</B>
 <P>
We present a computationally efficient method for deriving
the most appropriate transformation and mapping of a nested
loop for a given hierarchical parallel machine. This method
is in the context of our systematic and general theory of
unimodular loop transformations for the problem of iteration
space partitioning \cite{kandk6}. Finding an optimal mapping or
an optimal associated unimodular transformation is NP-complete.
We present a polynomial time method for obtaining a `good'
transformation using a simple parameterized model of the
hierarchical machine. We outline a systematic methodology
for obtaining the most appropriate mapping.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Li_Tandri_et">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Li_Tandri_et.ps.Z">Locality and Loop Scheduling on Numa Multiprocessors</A>
 <P>
<B>Authors:</B> Hui Li, Sudarsan Tandri Michael Stumm, and Kenneth C. Sevcik
 <P>
<B>Where:</B> International Conference on Parallel Processing 93
 <P>
<B>Keywords:</B> NUMA multiprocessors, Locality, Scheduling 
 <P>
<B>Abstract:</B>
 <P>
An important issue in the parallel execution of loops is how to
partition and schedule the loops onto the available processors.
While most existing dynamic scheduling algorithms manage load
imbalances well, they fail to take locality into account and
therefore perform poorly on parallel systems with non-uniform
memory access times.  In this paper, we propose a new loop
scheduling algorithm, Locality-based Dynamic Scheduling (LDS),
that exploits locality, and dynamically balances the load.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Sandhu_et_al_PPOPP">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Sandhu_et_al_PPOPP.ps.Z">The shared  regions  approach to software cache coherence on multiprocessors</A>
 <P>
<B>Authors:</B> Harjinder Sandhu, Benjamin Gamsa and Songnian Zhou 
 <P>
<B>Where:</B> Proceedings of  the  1993  ACM  SIGPLAN Symposium on
Principles and Pranctice of Parallel Programming, May (1993).
 <P>
<B>Keywords:</B>  NUMA, cache coherence, multiprocessor performance
 <P>
<B>Abstract:</B>
 <P>
The effective management of caches is critical to the performance of
applications on shared-memory multiprocessors. In this paper,
we discuss a technique for software cache coherence that is
based upon the integration of a program-level abstraction for shared data
with software cache management. The program-level abstraction,
called <EM>Shared Regions</EM>, explicitly relates synchronization objects
with the data they protect. Cache coherence algorithms are presented
which use the information provided by shared region primitives, and
ensure that shared regions are always cacheable by the processors accessing
them. Measurements and experiments of the Shared Region approach on a
shared-memory multiprocessor are shown. Comparisons with other software
based coherence strategies, including a user-controlled strategy and an
operating system-based strategy, show that this approach is able to
deliver better performance, with relatively low corresponding overhead
and only a small increase in the programming effort.  Compared to
a compiler-based coherence strategy, the Shared Regions
approach still performs better  than a compiler that can achieve 90\%
accuracy in allowing cacheing, as long as the regions are a few 
hundred bytes or larger, or they are re-used a few times in the cache.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Wilton_Vranesic_SPDP">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Wilton_Vranesic_SPDP.ps.Z">Architectural Support for Block Transfers in a Shared-Memory Multiprocessor</A>
 <P>
<B>Authors:</B> Steven J.E. Wilton and Zvonko G. Vranesic
 <P>
<B>Where:</B> Fifth IEEE Symposium on Parallel and Distributed Processing,
Irving, Texas, December 1993
 <P>
<B>Keywords:</B> Shared-memory multiprocessor, block transfer support
 <P>
<B>Abstract:</B>
 <P>
This paper examines how the performance of a shared-memory multiprocessor
can be improved by including hardware support for block transfers.  A system
similar to the Hector multiprocessor developed at the University of Toronto
is used as a base architecture.  It is shown that such hardware support can
improve the performance of initialization code by as much as 50%, but that
the amount of improvement depends on the memory access behavior of the
program and the way in which the operating system issues block transfer
requests.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Sevcik_Zhou_PERF93">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Sevcik_Zhou_PERF93.ps.Z">Performance Benefits and Limitations of Large NUMA Multiprocessors</A>
 <P>
<B>Authors:</B> Kenneth C. Sevcik and Songnian Zhou
 <P>
<B>Where:</B> Proceedings of Performance '93 , Rome, Italy, September 27 to October 1, 1993, pp. 183-204, Elsevier Science Publ.
 <P>
<B>Abstract:</B> Please see the postscript file.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Harz_Sevcik_SC93">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Harz_Sevcik_SC93.ps.Z">Hot Spot Analysis in Large Scale Shared Memory Multiprocessors</A>
 <P>
<B>Authors:</B> Karim Harzallah and Kenneth C. Sevcik
 <P>
<B>Where:</B> Proceedings of the Supercomputing '93 Conference, November, 1993, Portland, Oregon.
 <P>
<B>Abstract:</B> Please see the postscript file.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Sevcik_JPE">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Sevcik_JPE.ps.Z">Application Scheduling and Processor Allocation in Multiprogrammed Parallel Processing Systems</A>
 <P>
<B>Authors:</B> Kenneth C. Sevcik
 <P>
<B>Where:</B> (Journal of) Performance Evaluation, vol. 19 (1994), pp. 107-140
(Special issue on the performance evaluation of parallel systems)
 <P>
<B>Abstract:</B> Please see the postscript file.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Holliday_Stumm_IEEETC">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Holliday_Stumm_IEEETC.ps.Z">Performance Evaluation of Hierarchical Ring-Based Shared Memory Multiprocessors</A> 
 <P>
<B>Authors:</B> <BR>
Mark Holliday<BR>
Dept. of Computer Science, Duke University, Durham, NC 27706
 <P>
Michael Stumm<BR>
Dept. of Electrical and Computer Engineering<BR>
University of Toronto, Toronto, Canada M5S 1A4 
 <P>
<B>Date:</B> November 1992; revised April 1993
 <P>
<B>Where:</B> Technical Report CS-1992-18, Duke University<BR>
         IEEE Transactions on Computers
 <P>
<B>Keywords:</B> communication locality; hierarchical ring-based
networks; hot spots; large scale parallel systems; memory banks;
performance evaluation; prefetching; shared memory multiprocessors;
simulation.
 <P>
<B>Abstract:</B>
 <P>
	This paper investigates the performance of word-packet, slotted
	unidirectional ring-based hierarchical direct networks in the
	context of large-scale shared memory multiprocessors.
	Slotted unidirectional rings are attractive because their
	electrical characteristics and simple interfaces allow for fast
	cycle times and large bandwidths.
	For large-scale systems, it is necessary to use multiple rings
	for increased aggregate bandwidth.
	Hierarchies are attractive because the topology ensures unique
	paths between nodes, simple node interfaces and simple inter-ring
	connections.
 <P>
	To ensure that a realistic region of the design space is examined, 
	the architecture of the network used in the Hector prototype is 
	adopted as the initial design point.
	A simulator of that architecture has been developed and validated with
	measurements from the prototype.
	The system and workload parameterization reflects conditions
	expected in the near future.
 <P>
	The results of our study show the importance of system balance on 
	performance. Large-scale systems inherently have large
	communication delays for distant accesses, so processor efficiency
	will be low, unless the processors can operate with multiple 
	outstanding transactions using techniques such as prefetching, 
	asynchronous writes and multiple hardware contexts.
	However with multiple outstanding transactions and only one memory
	bank per processing module, memory quickly saturates.
	Memory saturation can be alleviated by having multiple memory
	banks per processing module, but this shifts the bottleneck to the
	ring subsystem.
	While the topology of the ring hierarchy affects performance,
	the ring subsystem will inherently limit the throughput of the system.
	Hence increasing the number of
	outstanding transactions per processor beyond a certain point only
	has a limiting effect on performance, since it causes some of the
	rings to become congested.
	An adaptive maximum number of outstanding
	transactions appears necessary to adjust for the appropriate tradeoff
	between concurrency and contention as the communication locality 
	changes. We show the relationships between processor, ring and memory 
	speeds, and their effects on performance.
	Using block transfers for prefetching seems unlikely to be advantageous
	in that the improvement in the cache hit ratio needed to compensate for
	the increased network utilization is substantial.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Curran_Stumm_CS">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Curran_Stumm_CS.ps.Z">A Comparison of basic CPU Scheduling Algorithms for Multiprocessor Unix</A> 
 <P>
<B>Authors:</B> Stephen Curran  and  Michael Stumm
 <P>
<B>Where:</B> Computer Systems, 3(4), Oct., 1990, pp. 551--579.
 <P>
<B>Abstract:</B>
 <P>
	In this paper, we present the results of a simulation study
	comparing three basic algorithms that schedule independent tasks in 
	multiprocessor versions of Unix.
	Two of these algorithms, namely Central Queue and Initial Placement,
	are obvious extensions to the standard uniprocessor scheduling 
	algorithm and are in use in a number of multiprocessor systems.
	A third algorithm, Take, is a variation on Initial Placement,
	where processors are allowed to raid the task queues of the other
	processors.
	Our simulation results show the difference between the
	performance of the three algorithms to be small when
	scheduling a typical Unix workload running on a small, bus-based,
	shared memory multiprocessor.
	They also show that the Take algorithm performs best for those
	multiprocessors on which tasks incur overhead each time they migrate.
	In particular, the Take algorithm appears to be more stable
	than the other two algorithms under extreme conditions.


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<HR>
<A NAME="Stumm_Unrau_Krieger_USENIX92">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Stumm_Unrau_Krieger
_USENIX92.ps.Z">Hierarchical Clustering: A Structure for Scalable Multiprocessor
 Operating System Design</A>
 <P>
<B>Authors:</B> Michael Stumm, Ron Unrau, and Orran Krieger
 <P>
<B>Where:</B> Extended version of Clustering Micro-Kernels for
Scalability, Proc. of the Usenix Workshop on Micro-Kernels and Other
Kernel Architectures, April, 1992.
 <P>
<B>Abstract:</B> Please see the postscript file.
 <P>

<!--------------------------------------------------------------------->
<HR>
<A NAME="Stumm_Vranesic_White_IPPS93">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Stumm_Vranesic_White_IPPS93.ps.Z">Experience with the Hector Multiprocessor</A>
 <P>
<B>Authors:</B> Michael Stumm, Zvonko Vranesic, Ron White
 <P>
<B>Where:</B> Extended version of paper with same title in Proc. Intl. Parallel Processing Symposium Parallel Systems Fair, 1993, pp. 9-16.
 <P>
<B>Abstract:</B> Please see the postscript file.
 <P>

<!--------------------------------------------------------------------->
<HR>
<A NAME="Krieger_etal_IEEEComp94">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Krieger_etal_IEEEComp94.ps.Z">The Alloc Stream Facility: A redesign of application-level Strea
m I/O</A>
 <P>
<B>Authors:</B> O. Krieger, M. Stumm, and R. Unrau
 <P>
<B>Where:</B>IEEE Computer, 27(3), March, 1994, pp. 75--83.
 <P>
<B>Abstract:</B>
 <P>
  This paper introduces a new application level I/O facility
  called the Alloc Stream Facility (ASF).  ASF has several
  key advantages.  First, performance is substantially improved
  as a result of a)~the structure of the facility that allows it
  to take advantage of system specific features like mapped
  files, and b)~a reduction in data copying and the number of I/O
  system calls.  Second, the facility is designed for
  multi-threaded applications running on multiprocessors and
  allows for a high degree of concurrency.  Finally, the facility
  can support a variety of I/O interfaces, including stdio,
  emulated Unix I/O, ASI, and C++ streams, in a
  way that allows applications to freely intermix calls to the
  different interfaces, resulting in improved code re-usability.

  We show that on several Unix workstation platforms, I/O
  intensive applications perform substantially better when linked
  to ASF instead of the native facilities -- in the best case, up
  to twice as good. Modifying the applications to use a new
  interface provided with ASF can improve performance even more.
<P>

<!--------------------------------------------------------------------->
<HR>
<A NAME="Krieger_Stumm_DAGS93">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Krieger_Stumm_DAGS93.ps.Z">HFS: A Flexible File System for Large-Scale Multiprocessors</A>
 <P>
<B>Authors:</B> Orran Krieger and Michael Stumm
 <P>
<B>Where:</B> Proceedings of the 1993 DAGS/PC Symposium
 <P>
<B>Abstract:</B>
 <P>
The Hurricane File System (HFS) is a new file system
  being developed for large-scale shared memory multiprocessors with
  distributed disks. The main goal of this file system is scalability; that is,
  the file system is designed to handle demands that are expected to grow
  linearly with the number of processors in the system. To achieve this goal,
  HFS is designed using a new structuring technique called Hierarchical
  Clustering. HFS is also designed to be flexible in supporting a variety of
  policies for managing file data and for managing file system state. This
  flexibility is necessary to support in a scalable fashion the diverse
  workloads we expect for a multiprocessor file system.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Krieger_etal_ICPP93">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Krieger_etal_ICPP93.ps.Z">A Fair Fast Scalable Reader-Writer Lock</A>
 <P>
<B>Authors:</B> O. Krieger, M. Stumm, R. Unrau, and J. Hanna
 <P>
<B>Where:</B> Proc. Intl. Conf. on Parallel Processing, 1993.
 <P>
<B>Abstract:</B>
 <P>
A reader-writer lock allows either multiple readers to inspect
  shared data or a single writer exclusive access to that data.  On
  shared memory multiprocessors, the cost of acquiring and
  releasing these locks can have a large impact on the performance
  of parallel applications.  Other researchers have shown how to
  implement scalable locks, that is, locks that can become
  contended without resulting in memory or interconnection network
  contention.  This paper describes a new algorithm for a
  reader-writer lock that, while being scalable in the contended
  case, has a low overhead in the uncontended case.  This is
  important because most parallel applications are written so that
  locks are typically uncontended.  The only atomic operation
  required by this algorithm is fetch_and_store and hence
  it can be used on most current multiprocessor systems.
  Experimental results are provided.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Kulkarni_Stumm_Tut">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Kulkarni_Stumm_Tutorial.ps.Z">Loop and Data Transformations: A tutorial</A>
 <P>
<B>Authors:</B> Dattatraya Kulkarni and Michael Stumm
 <P>
<B>Where:</B> CSRI Tech Report 337, University of Toronto, June 1993.
 <P>
<B>Abstract:</B>
 <P>
Hierarchically structured machines appear to be becoming the
dominant parallel computing structure. These systems have
non-uniform access times. We address the problem of restructuring
a possibly sequential program to execute efficiently on such
parallel machines. This restructuring involves transforming and
partitioning the loop structures and the data to so as to improve
<EM>parallelism</EM>, <EM>static</EM> and <EM>dynamic locality</EM>, and
<EM>load balance</EM>.
The objective of this paper is to present previous and ongoing work
on loop and data transformations and motivate a <EM>unified</EM> framework to
restructuring of a sequence of loops and data so as to execute efficiently on
parallel machines with several levels of hierarchy.


<!--------------------------------------------------------------------->
<HR>
<A NAME="Baru_Zilio_PADS93">.</A>
<HR>

<B>Title:</B> <A HREF="./../../manually_copied_ftp_colon_doubleslash_ftp_cs_toronto_edu/parallel/Baru_Zilio_PADS93.ps.Z">Data reorganization in parallel database systems</A>
 <P>
<B>Authors:</B> Chaitanya Baru & Daniel C. Zilio
 <P>
<B>Where:</B> Proc. of the IEEE Workshop on Advances in Parallel and
Distributed Systems}, Princeton, NJ, pp.102-107, Oct.  1993. 
 <P>
<B>Abstract:</B>
 <P>
Parallel database systems are suitable for use in
applications with high capacity and high performance and availability
requirements.  The trend in such systems is to provide efficient
<